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rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ad7851 ? analog devices, inc., 1996 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 fax: 617/326-8703 functional block diagram ain (+) ain (? c ref1 c ref2 cal av dd agnd agnd dv dd dgnd amode clkin sleep convst busy sync sm1 sm2 din dout sclk polarity charge redistribution dac comp 4.096 v reference ad7851 buf t/h sar + adc control calibration memory and controller serial interface / control register ref in / ref out 14-bit 333 ksps serial a/d converter features single 5 v supply 333 ksps throughput rate/ 6 2 lsb dnla grade 285 ksps throughput rate/ 6 1 lsb dnlk grade a & k grades guaranteed to 125 8 c/238 ksps throughput rate pseudo-differ ential input with two input ranges system and self-calibration with autocalibration on power-up read/write capability of calibration data low power: 60 mw typ power-down mode: 5 m w typ power consumption flexible serial interface: 8051/spi/qspi/ m p compatible 24-pin dip, soic and ssop packages applications digital signal processing speech recognition and synthesis spectrum analysis dsp servo control instrumentation and control systems high speed modems automotive general description the ad7851 is a high speed, 14-bit adc that operates from a single 5 v power supply. the adc powers-up with a set of default conditions at which time it can be operated as a read- only adc. the adc contains self-calibration and system- calibration options to ensure accurate operation over time and temperature and has a number of power-down options for low power applications. the ad7851 is capable of 333 khz throughput rate. the input track-and-hold acquires a signal in 0.33 m s and features a pseudo-differential sampling scheme. the ad7851 has the added advantage of two input voltage ranges (0 v to v ref, and Cv ref /2 to +v ref /2 centered about v ref /2). input signal range is to v dd and the part is capable of converting full-power signals to 20 mhz. cmos construction ensures low power dissipation (60 mw typ) with power-down mode (5 m w typ). the part is available in 24- pin, 0.3 inch-wide dual-in-line package (dip), 24-lead small outline (soic) and 24-lead small shrink outline (ssop) packages. * patent pending. see page 35 for data sheet index. product highlights 1. single 5 v supply. 2. operates with reference voltages from 4 v to v dd . 3. analog input ranges from 0 v to v dd . 4. system and self-calibration including power-down mode. 5. versatile serial i/o port.
rev. a C2C ad7851Cspecifications 1, 2 a grade: f clkin = 7 mhz (C40 8 c to +85 8 c), f sample = 333 khz; k grade: f clkin = 6 mhz (0 8 c to +85 8 c), f sample = 285 khz; a and k grade: f clkin = 5 mhz (to +125 8 c), f sample = 238 khz; (av dd = dv dd = +5.0 v 6 5%, ref in /ref out = 4.096 v external reference; s leep = logic high; t a = t min to t max , unless otherwise noted) parameter a 1 k 1 units test conditions/comments dynamic performance signal-to-noise + distortion ratio 3 (snr) 77 78 db min typically snr is 79.5 db v in = 10 khz, sine wave, f sample = 333 khz total harmonic distortion (thd) C86 C86 db max v in = 10 khz, sine wave, f sample = 333 khz, typically C96 db peak harmonic or spurious noise C87 C87 db max v in = 10 khz, f sample = 333 khz intermodulation distortion (imd) second order terms C86 C90 db typ fa = 9.983 khz, fb = 1 0.05 khz, f sample = 333 khz third order terms C86 C90 db typ fa = 9.983 khz, fb = 1 0.05 khz, f sample = 333 khz full power bandwidth 20 20 mhz typ @ 3 db dc accuracy resolution 14 14 bits integral nonlinearity 2 1 lsb max differential nonlinearity 2 1 lsb max guaranteed no missed codes to 14 bits unipolar offset error 10 10 lsb max review: adjusting the offset calibration positive full-scale error 10 10 lsb max register in the calibration registers section negative full-scale error 10 10 lsb typ of the data sheet. bipolar zero error 1 1 lsb typ analog input input voltage ranges 0 v to v ref 0 v to v ref volts i .e., ain (+) C ain(C) = 0 v to v ref , ain(C) can be biased up but ain(+) cannot go below ain(C). v ref /2 v ref /2 volts i.e., ain(+) C ain(C) = Cv ref /2 to +v ref /2, ain(C) should be biased up and ain(+) can go below ain(C) but cannot go below 0 v. leakage current 1 1 m a max input capacitance 20 20 pf typ reference input/output ref in input voltage range 4/v dd 4/v dd v min/max functional from 1.2 v input impedance 150 150 k w typ resistor connected to internal reference node ref out output voltage 3.696/4.496 3.696/4.496 v min/max ref out tempco 50 50 ppm/ c typ logic inputs input high voltage, v inh v dd C 1.0 v dd C 1.0 v min input low voltage, v inl 0.4 0.4 v max input current, i in 10 10 m a max v in = 0 v or v dd input capacitance, c in 5 10 10 pf max logic outputs output high voltage, v oh v dd C 0.4 v dd C 0.4 v min i source = 200 m a output low voltage, v ol 0.4 0.4 v max i sink = 0.8 ma floating-state leakage current 10 10 m a max floating-state output capacitance 5 10 10 pf max output coding straight (natural) binary unipolar input range 2s complement bipolar input range conversion rate conversion time 2.78 3.25 m s max 19.5 clkin cycles conversion + t/h acquisition time 3.0 3.5 m s max 21 clkin cycles throughput rate
ad7851 C3C rev. a parameter a 1 k 1 units test conditions/comments power performance av dd, dv dd +4.75/+5.25 +4.75/+5.25 v min/max i dd normal mode 5 17 17 ma max av dd = dv dd = 4.75 v to 5.25 v. typically 12 ma. sleep mode 6 with external clock on 20 20 m a typ full power-down. power management bits in control register set as pmgt1 = 1, pmgt0 = 0. 600 600 m a typ partial power-down. power management bits in control register set as pmgt1 = 1, pmgt0 = 1. with external clock off 10 10 m a max typically 1 m a. full power-down. power management bits in control register set as pmgt1 = 1, pmgt0 = 0. 300 300 m a typ partial power-down. power management bits in control register set as pmgt1 = 1, pmgt0 = 1. normal mode power dissipation 89.25 89.25 mw max v dd = 5.25 v: typically 63 mw; sleep = v dd . sleep mode power dissipation with external clock on 105 105 m w typ v dd = 5.25 v; sleep = 0 v with external clock off 52.5 52.5 m w max v dd = 5.25 v; typically 5.25 m w; sleep = 0 v system calibration offset calibration span 7 +0.05 v ref /C0.05 v ref v max/min allowable offset voltage span for calibration gain calibration span 7 +1.025 v ref /C0.975 v ref v max/min allowable full-scale voltage span for calibratio n notes 1 temperature ranges as follows: a version, C40 c to +125 c; k version, 0 c to +125 c. 2 specifications apply after calibration. 3 snr calculation includes distortion and noise components. 4 sample tested @ +25 c to ensure compliance. 5 all digital inputs @ dgnd except for convst , sleep , cal , and sync @ dv dd . no load on the digital outputs. analog inputs @ agnd. 6 clkin @ dgnd when external clock off. all digital inputs @ dgnd except for convst , sleep , cal , and sync @ dv dd . no load on the digital outputs. analog inputs @ agnd. 7 the offset and gain calibration spans are defined as the range of offset and gain errors that the ad7851 can calibrate. note also that these are voltage spans and are not absolute voltages (i.e., the allowable system offset voltage presented at ain(+) for the system offset error to be adjusted out will be ain(C) 0.05 v ref , and the allowable system full-scale voltage applied between ain(+) and ain(C) for the system full-scale voltage error to be adjusted out will be v ref 0.025 v ref ). this is explained in more detail in the calibration section of the data sheet. specifications subject to change without notice.
ad7851 C4C rev. a limit at t min , t max parameter a, k units description f clkin 2 500 khz min master clock frequency 7 mhz max f sclk 3 10 mhz max interface modes 1, 2, 3 (external serial clock) f clk in mhz max interface modes 4, 5 (internal serial clock) t 1 4 100 ns min convst pulse width t 2 50 ns max convst to busy - propagation delay t convert 3.25 m s max conversion time = 20 t clkin t 3 C0.4 t sclk ns min sync to sclk setup time (noncontinuous sclk input) 0.4 t sclk ns min/max sync to sclk setup time (continuous sclk input) t 4 0.6 t sclk ns min sync to sclk setup time. interface mode 4 only t 5 5 30 ns max delay from sync until dout 3-state disabled t 5a 5 30 ns max delay from sync until din 3-state disabled t 6 5 45 ns max data access time after sclk t 7 30 ns min data setup time prior to sclk - t 8 20 ns min data valid to sclk hold time t 9 6 0.4 t sclk ns min sclk high pulse width (interface modes 4 and 5) t 10 6 0.4 t sclk ns min sclk low pulse width (interface modes 4 and 5) t 11 30 ns min sclk - to sync - hold time (noncontinuous sclk) 30/0.4 t sclk ns min/max (continuous sclk) does not apply to interface mode 3 t 11a 50 ns max sclk - to sync - hold time t 12 7 50 ns max delay from sync - until dout 3-state enabled t 13 90 ns max delay from sclk - to din being configured as output t 14 8 50 ns max delay from sclk - to din being configured as input t 15 2.5 t clkin ns max cal - to busy - delay t 16 2.5 t clkin ns max convst to busy - delay in calibration sequence t cal 9 41.7 ms typ full self-calibration time, master clock dependent (250026 t clkin ) t cal1 9 37.04 ms typ internal dac plus system full-scale cal time, master clock dependent (222228 t clkin ) t cal2 9 4.63 ms typ system offset calibration time, master clock dependent (27798 t clkin ) t delay 65 ns max delay from clk to sclk notes descriptions that refer to sclk - (rising) or sclk (falling) edges here are with the polarity pin high. for the polarity pin low then the opposite edge of sclk will apply. 1 sample tested at +25 c to ensure compliance. all input signals are specified with tr = tf = 5 ns (10% to 90% of v dd ) and timed from a voltage level of 1.6 v. see table x and timing diagrams for different interface modes and calibration. 2 mark/space ratio for the master clock input is 40/60 to 60/40. 3 for interface modes 1, 2, 3 the sclk max frequency will be 10 mhz. for interface modes 4 and 5 the sclk will be an output and the frequency will be f clkin . 4 the convst pulse width will here only apply for normal operation. when the part is in power-down mode, a different convst pulse width will apply (see power- down section). 5 measured with the load circuit of figure 1 and defined as the time required for the output to cross 0.8 v or 2.4 v. 6 for self-clocking mode (interface modes 4, 5) the nominal sclk high and low times will be 0.5 t sclk = 0.5 t clkin . 7 t 12 is derived from the measured time taken by the data outputs to change 0.5 v when loaded with the circuit of figure 1. the measured number is then extrapolated back to remove the effects of charging or discharging the 50 pf capacitor. this means that the time, t 12 , quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the bus loading. 8 t 14 is derived form the measured time taken by the data outputs to change 0.5 v when loaded with the circuit of figure 1. the measured number is then extrapolated back to remove the effects of charging or discharging the 50 pf capacitor. this means that the time quoted in the timing characteristics is the true delay of the part in turning off the output drivers and configuring the din line as an input. once this time has elapsed the user can drive the din line knowing that a bus conflict will not occur. 9 the typical time specified for the calibration times is for a master clock of 6 mhz. specifications subject to change without notice. timing specifications 1 (av dd = dv dd = +5.0 v 6 5%; f clkin = 6 mhz, t a = t min to t max , unless otherwise noted)
C5C rev. a ad7851 typical timing diagrams figures 2 and 3 show typical read and write timing diagrams. figure 2 shows the reading and writing after conversion in in- terface modes 2 and 3. to attain the maximum sample rate of 285 khz in interface modes 2 and 3, reading and writing must be performed during conversion. figure 3 shows the timing dia- gram for interface modes 4 and 5 with sample rate of 285 khz. at least 330 ns acquisition time must be allowed (the time from the falling edge of busy to the next rising edge of convst ) before the next conversion begins to ensure that the part is settled to the 14-bit level. if the user does not want to provide the convst signal, the conversion can be initiated in software by writing to the control register. 1.6ma +2.1v 200? c l 50pf to output pin i ol i oh figure 1. load circuit for digital output timing specifications db15 db0 db11 polarity pin logic high sync (i/p) sclk (i/p) t 3 busy (o/p) convst (i/p) t 2 t 5 t 11 t 6 t 9 t 10 15 6 16 t 12 dout (o/p) db0 db11 t 8 din (i/p) 3-state 3-state db15 t convert t convert = 3.25? max, t 1 = 100ns min, t 5 = 30ns max, t 7 = 30ns min t 1 t 6 t 7 figure 2. ad7851 timing diagram (typical read and write operation for interface modes 2, 3) polarity pin logic high sync ( o/p) sclk (o/p) t 4 busy (o/p) convst (i/p) t 2 t 5 t 11 t 12 t 9 t 10 15 6 16 dout (o/p) db0 db11 t 8 din (i/p) db15 db0 3-state db11 3-state db15 t convert t convert = 3.25? max, t 1 = 100ns min, t 5 = 30ns max, t 7 = 30ns min t 1 t 6 t 7 figure 3. ad7851 timing diagram (typical read and write operation for interface modes 4, 5)
ad7851 C6C rev. a absolute maximum ratings 1 (t a = +25 c unless otherwise noted) av dd to agnd . . . . . . . . . . . . . . . . . . . . . . . . C0.3 v to +7 v dv dd to dgnd . . . . . . . . . . . . . . . . . . . . . . . C0.3 v to +7 v av dd to dv dd . . . . . . . . . . . . . . . . . . . . . . . C0.3 v to +0.3 v analog input voltage to agnd . . . . C0.3 v to av dd + 0.3 v digital input voltage to dgnd . . . . C0.3 v to dv dd + 0.3 v digital output voltage to dgnd . . . C0.3 v to dv dd + 0.3 v ref in /ref out to agnd . . . . . . . . . C0.3 v to av dd + 0.3 v input current to any pin except supplies 2 . . . . . . . . 10 ma operating temperature range commercial (a, k versions) . . . . . . . . . . C40 c to +125 c storage temperature range . . . . . . . . . . . C65 c to +150 c junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150 c plastic dip package, power dissipation . . . . . . . . . . 450 mw q ja thermal impedance . . . . . . . . . . . . . . . . . . . . 105 c/w q jc thermal impedance . . . . . . . . . . . . . . . . . . . . 34.7 c/w lead temperature, (soldering, 10 secs) . . . . . . . . . . +260 c soic, ssop package, power dissipation . . . . . . . . . 450 mw q ja thermal impedance . . . 75 c/w (soic) 115 c/w (ssop) q jc thermal impedance . . . . 25 c/w (soic) 35 c/w (ssop) lead temperature, soldering vapor phase (60 secs) . . . . . . . . . . . . . . . . . . . . . . +215 c infrared (15 secs) . . . . . . . . . . . . . . . . . . . . . . . . . +220 c esd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >1.5 kv notes 1 stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 transient currents of up to 100 ma will not cause scr latch-up. pinout for dip, soic and ssop 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 ad7851 top view (not to scale) convst busy sleep ref in /ref out av dd agnd c ref 1 c ref 2 ain(+) ain(? nc agnd sync sclk clkin din dout dgnd dv dd cal sm2 sm1 polarity amode ordering guide 1 linearity temp error throughput throughput package model range (lsb) 2 rate @ +125 8 c options 3 ad7851an C40 c to +85 c 2 333 ksps 238 ksps n-24 ad7851kn 0 c to +85 c 1 285 ksps 238 ksps n-24 ad7851ar C40 c to +85 c 2 333 ksps 238 ksps r-24 ad7851kr 0 c to +85 c 1 285 ksps 238 ksps r-24 ad7851ars C40 c to +85 c 2 333 ksps 238 ksps rs-24 EVAL-AD7851CB 4 eval-control board 5 notes 1 both a and k grades are guaranteed up to 125 c, but at a lower throughput of 238 khz (5 mhz). . 2 linearity error refers to the integral linearity error. 3 n = plastic dip; r = soic; rs = ssop. 4 this can be used as a stand-alone evaluation board or in conjunction with the eval-control board for evaluation/demonstration purposes. 5 this board is a complete unit allowing a pc to control and communicate with all analog devices, inc. evaluation boards ending in the cb designators.
C7C rev. a ad7851 terminology integral nonlinearity this is the maximum deviation from a straight line passing through the endpoints of the adc transfer function. the end- points of the transfer function are zero scale, a point 1/2 lsb below the first code transition, and full scale, a point 1/2 lsb above the last code transition. differential nonlinearity this is the difference between the measured and the ideal 1 lsb change between any two adjacent codes in the adc. total unadjusted error this is the deviation of the actual code from the ideal code tak- ing all errors into account ( gain, offset, integral nonlinearity, and other errors ) at any point along the transfer function. unipolar offset error this is the deviation of the first code transition (00 . . . 000 to 00 . . . 001) from the ideal ain(+) voltage (ain(C) + 1/2 lsb) when operating in the unipolar mode. positive full-scale error this applies to the unipolar and bipolar modes and is the devia- tion of the last code transition from the ideal ain(+) voltage (ain(C) + full scale C 1.5 lsb) after the offset error has been adjusted out. negative full-scale error this applies to the bipolar mode only and is the deviation of the first code transition (00 . . . 000 to 00 . . . 001) from the ideal ain(+) voltage (ain(C) C v ref /2 + 0.5 lsb). bipolar zero error this is the deviation of the midscale transition (all 0s to all 1s) from the ideal ain(+) voltage (ain(C) C 1/2 lsb). track/hold acquisition time the track/hold amplifier returns into track mode and the end of conversion. track/hold acquisition time is the time required for the output of the track/hold amplifier to reach its final value, within 1/2 lsb, after the end of conversion. signal to (noise + distortion) ratio this is the measured ratio of signal to (noise + distortion) at the output of the a/d converter. the signal is the rms amplitude of the fundamental. noise is the sum of all nonfundamental sig- nals up to half the sampling frequency (f s /2), excluding dc. the ratio is dependent on the number of quantization levels in the digitization process; the more levels, the smaller the quantiza- tion noise. the theoretical signal to (noise + distortion) ratio for an ideal n-bit converter with a sine wave input is given by: signal to (noise + distortion) = ( 6.02 n + 1.76 )db thus for a 14-bit converter, this is 86 db. total harmonic distortion total harmonic distortion (thd) is the ratio of the rms sum of harmonics to the fundamental. for the ad7851, it is defined as: thd ( db ) = 20log v 2 2 + v 3 2 + v 4 2 + v 5 2 + v 6 2 ? ? ? v 1 where v 1 is the rms amplitude of the fundamental and v 2 , v 3 , v 4 , v 5 and v 6 are the rms amplitudes of the second through the sixth harmonics. peak harmonic or spurious noise peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the adc output spectrum (up to f s /2 and excluding dc) to the rms value of the fundamental. normally, the value of this specification is deter- mined by the largest harmonic in the spectrum, but for parts where the harmonics are buried in the noise floor, it will be a noise peak. intermodulation distortion with inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities will create distortion products at sum and difference frequencies of mfa nfb where m, n = 0, 1, 2, 3, etc. intermodulation distortion terms are those for which neither m nor n are equal to zero. for example, the second order terms include (fa + fb) and (fa C fb), while the third order terms include (2fa + fb), (2fa C fb), (fa + 2fb) and (fa C 2fb). testing is performed using the ccif standard where two input frequencies near the top end of the input bandwidth are used. in this case, the second order terms are usually distanced in fre- quency from the original sine waves while the third order terms are usually at a frequency close to the input frequencies. as a result, the second and third order terms are specified separately. the calculation of the intermodulation distortion is as per the thd specification where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals expressed in dbs. power supply rejection ratio power supply rejection ratio (psrr) is defined as the ratio of the power in adc output at frequency f to the power of the full- scale sine wave applied to the supply voltage (v dd ). the units are in lsb, %of fs per % of supply voltage, or expressed loga- rithmically, in db (psrr (db) = 10 log(pf/pfs)). full power bandwidth the full power bandwidth (fpbw) is that frequency at which the amplitude of the reconstructed (using ffts) fundamental (neglecting harmonics and snr) is reduced by 3 db for a full- scale input.
ad7851 C8C rev. a pin function description pin mnemonic description 1 convst convert start. logic input. a low to high transition on this input puts the track/hold into its hold mode and starts conversion. when this input is not used, it should be tied to dv dd . 2 busy busy output. the busy output is triggered high by the falling edge of convst or rising edge of cal , and remains high until conversion is completed. busy is also used to indicate when the ad7851 has completed its on-chip calibration sequence. 3 sleep sleep input/low power mode. a logic 0 initiates a sleep and all circuitry is powered down including the in- ternal voltage reference provided there is no conversion or calibration being performed. calibration data is retained. a logic 1 results in normal operation. see power-down section for more details. 4 ref in / reference input/output. this pin is connected to the internal reference through a series resistor and is the ref out reference source for the analog-to-digital converter. the nominal reference voltage is 4.096 v and this ap- pears at the pin. this pin can be overdriven by an external reference or can be taken as high as av dd . when this pin is tied to av dd , then the c ref1 pin should also be tied to av dd . 5av dd analog positive supply voltage, +5.0 v 5%. 6, 12 agnd analog ground. ground reference for track/hold, reference and dac. 7c ref1 reference capacitor (0.01 m f ceramic disc in parallel with a 470 nf npo type). this external capacitor is used as a charge source for the internal dac. the capacitor should be tied between the pin and agnd. 8c ref2 reference capacitor (0.01 m f ceramic disc in parallel with a 470 nf npo type). this external capacitor is used in conjunction with the on-chip reference. the capacitor should be tied between the pin and agnd. 9 ain(+) analog input. positive input of the pseudo-differential analog input. cannot go below agnd or above av dd at any time, and cannot go below ain(C) when the unipolar input range is selected. 10 ain(C) analog input. negative input of the pseudo-differential analog input. cannot go below agnd or above av dd at any time. 11 nc no connect pin. 13 amode analog mode pin. this pin allows two different analog input ranges to be selected. a logic 0 selects range 0 to v ref (i.e., ain(+) C ain(C) = 0 to v ref ). in this case ain(+) cannot go below ain(C) and ain(C) cannot go below agnd. a logic 1 selects range Cv ref /2 to +v ref /2 (i.e., ain(+) C ain(C) = Cv ref /2 to +v ref /2). in this case ain(+) cannot go below agnd so that ain(C) needs to be biased to +v ref /2 to allow ain(+) to go from 0 v to +v ref v. 14 polarity serial clock polarity. this pin determines the active edge of the serial clock (sclk). toggling this pin will reverse the active edge of the serial clock (sclk). a logic 1 means that the serial clock (sclk) idles high and a logic 0 means that the serial clock (sclk) idles low. it is best to refer to the timing diagrams and table x for the sclk active edges. 15 sm1 serial mode select pin. this pin is used in conjunction with the sm2 pin to give different modes of opera- tion as described in table xi. 16 sm2 serial mode select pin. this pin is used in conjunction with the sm1 pin to give different modes of opera- tion as described in table xi. 17 cal calibration input. this pin has an internal pull-up current source of 0.15 m a. a logic 0 on this pin resets all logic and initiates a calibration on its rising edge. there is the option of connecting a 10 nf capacitor from this pin to agnd to allow for an automatic self calibration on power-up. this input overrides all other internal operations. 18 dv dd digital supply voltage, +5.0 v 5%. 19 dgnd digital ground. ground reference point for digital circuitry. 20 dout serial data output. the data output is supplied to this pin as a 16-bit serial word. 21 din serial data input. the data to be written is applied to this pin in serial form (16-bit word). this pin can act as an input pin or as a i/o pin depending on the serial interface mode the part is in (see table xi). 22 clkin master clock signal for the device (6 mhz or 7 mhz). sets the conversion and calibration times. 23 sclk serial port clock. logic input/output. the sclk pin is configured as an input or output, dependent on the type of serial data transmission (self-clocking or external-clocking) that has been selected by the sm1 and sm2 pins. the sclk idles high or low depending on the state of the polarity pin. 24 sync this pin can be an input level triggered active low (similar to a chip select in one case and to a frame sync in the other) or an output (similar to a frame sync) pin depending on sm1, sm2 (see table xi ) .
C9C rev. a ad7851 ad7851 on-chip registers the ad7851 powers up with a set of default conditions, and the user need not ever write to the device. in this case the ad7851 will operate as a read-only adc. the ad7851 still retains the flexibility for performing a full power-down, and a full self-calibration. note that the din pin should be tied to dgnd for operating the ad7851 as a read-only adc. extra features and flexibility such as performing different power-down options, different types of calibrations including system cali- bration, and software conversion start can be selected by writing to the part. the ad7851 contains a control register , adc output data register , status register , test register and 10 calibration regis- ters . the control register is write-only, the adc output data register and the status register are read-only, and the test and calibra- tion registers are both read/write registers. the test register is used for testing the part and should not be written to. addressing the on-chip registers writing a write operation to the ad7851 consists of 16 bits. the two msbs, addr0 and addr1, are decoded to determine which register is addressed, and the subsequent 14 bits of data are written to the addressed register. it is not until all 16 bits are written that the data is latched into the addressed register. table i shows the decoding of the address bits, while figure 4 shows the overall write reg- ister hierarchy. table i. write register addressing addr1 addr0 comment 0 0 this combination does not address any register so the subsequent 14 data bits are ignored. 0 1 this combination addresses the test register . the subsequent 14 data bits are written to the test register. 1 0 this combination addresses the calibration registers . the subsequent 14 data bits are written to the selected calibration register. 1 1 this combination addresses the control register . the subsequent 14 data bits are written to the control register. reading to read from the various registers the user must first write to bits 6 and 7 in the control register, rdslt0 and rdslt1. these bits are decoded to determine which register is addressed during a read operation. table ii shows the decoding of the read address bits while figure 5 shows the overall read register hierarchy. the power-up status of these bits is 00 so that the default read will be from the adc output data register. once the read selection bits are set in the control register all subsequent read operations that follow will be from the selected register until the read selection bits are changed in the control register. table ii. read register addressing rdslt1 rdslt0 comment 0 0 all successive read operations will be from adc output data register . this is the power-up de- fault setting. there will always be four leading zeros when reading from the adc output data register. 0 1 all successive read operations will be from test register . 1 0 all successive read operations will be from calibration registers . 1 1 all successive read operations will be from status register . addr1, addr0 decode test register control register gain (1) offset (1) dac (8) gain (1) offset (1) offset (1) gain (1) 01 10 11 00 01 10 11 calslt1, calslt0 decode calibration registers figure 4. write register hierarchy/address decoding rdslt1, rdslt0 decode test register calibration registers status register gain (1) offset (1) dac (8) gain (1) offset (1) offset (1) gain (1) 01 10 11 00 01 10 11 calslt1, calslt0 decode adc output data register 00 figure 5. read register hierarchy/address decoding
ad7851 C10C rev. a control register the arrangement of the control register is shown below. the control register is a write only register and contains 14 bits of data. the control register is selected by putting two 1s in addr1 and addr0. the function of the bits in the control register are described below. the power-up status of all bits is 0. msb zero zero zero zero pmgt1 pmgt0 pmgt1 rdslt0 2/ 3 mode convst calmd calst1 calslt0 stcal lsb control register bit function description bit mnemonic comment 13 zero these four bits must be set to 0 when writing to the control register. 12 zero 11 zero 10 zero 9 pmgt1 power management bits. these two bits are used with the sleep pin for putting the part into various 8 pmgt0 power-down modes (see power-down section for more details). 7 rdslt1 theses two bits determine which register is addressed for the read operations. see table ii. 6 rdslt0 52/ 3 mode interface mode select bit. with this bit set to 0, interface mode 2 is enabled. with this bit set to 1, interface mode 1 is enabled where din is used as an output as well as an input. this bit is set to 0 by default after every read cycle; thus when using interface mode 1, this bit needs to be set to 1 in every write cycle. 4 convst conversion start bit. a logic one in this bit position starts a single conversion, and this bit is automati- cally reset to 0 at the end of conversion. this bit may also used in conjunction with system calibration (see calibration section on page 21). 3 calmd calibration mode bit. a 0 here selects self-calibration and a 1 selects a system calibration (see table iii). 2 calslt1 calibration selection bits and start calibration bit. these bits have two functions. 1 calslt0 with the stcal bit set to 1, the calslt1 and calslt0 bits determine the type of calibration per- 0 stcal formed by the part (see table iii). the stcal bit is automatically reset to 0 at the end of calibration. with the stcal bit set to 0, the calslt1 and calslt0 bits are decoded to address the calibration register for read/write of calibration coefficients (see section on the calibration registers for more details). table iii. calibration selection calmd calslt1 calslt0 calibration type 00 0 a full internal calibration is initiated where the internal dac is calibrated followed by the internal gain error and finally the internal offset error is calibrated out. this is the default setting. 0 0 1 here the internal gain error is calibrated out followed by the internal offset error calibrated out. 0 1 0 this calibrates out the internal offset error only. 0 1 1 this calibrates out the internal gain error only. 10 0 a full system calibration is initiated here where first the internal dac is calibrated, fol- lowed by the system gain error, and finally the system offset error is calibrated out. 1 0 1 here the system gain error is calibrated out followed by the system offset error . 1 1 0 this calibrates out the system offset error only. 1 1 1 this calibrates out the system gain error only.
C11C rev. a ad7851 status register the arrangement of the status register is shown below. the status register is a read-only register and contains 16 bits of data. the status register is selected by first writing to the control register and putting two 1s in rdslt1 and rdslt0. the function of the bits in the status register are described below. the power-up status of all bits is 0. write to control register setting rdslt0 = rdslt1 = 1 read status register start figure 6. flowchart for reading the status register msb zero busy zero zero zero zero pmgt1 pmgt0 rdslt1 rdslt0 2/ 3 mode x calmd calslt1 calslt0 stcal lsb status register bit function description bit mnemonic comment 15 zero this bit is always 0. 14 busy conversion/calibration busy bit. when this bit is 1, this indicates that there is a conversion or calibration in progress. when this bit is 0, there is no conversion or calibration in progress. 13 zero these four bits are always 0. 12 zero 11 zero 10 zero 9 pmgt1 power management bits. these bits along with the sleep pin will indicate if the part is in a power-down 8 pmgt0 mode or not. see table vi in power-down section for description. 7 one both these bits are always 1 indicating it is the status register that is being read. see table ii. 6 one 52/ 3 mode interface mode select bit. with this bit 0, the device is in interface mode 2. with this bit 1, the device is in interface mode 1. this bit is reset to 0 after every read cycle. 4 x dont care bit. 3 calmd calibration mode bit. a 0 in this bit indicates a self-calibration is selected, and a 1 in this bit indicates a system calibration is selected (see table iii). 2 calslt1 calibration selection bits and start calibration bit. the stcal bit is read as a 1 if a calibration is in 1 calslt0 progress and as a 0 if there is no calibration in progress. the calslt1 and calslt0 bits indicate 0 stcal which of the calibration registers are addressed for reading and writing (see section on the calibration registers for more details).
ad7851 C12C rev. a calibration registers the ad7851 has 10 calibration registers in all, 8 for the dac, 1 for the offset and 1 for gain. data can be written to or read from all 10 calibration registers. in self and system calibration the part automatically modifies the calibration registers; only if the user needs to modify the calibration registers should an attempt be made to read from and write to the calibration registers. addressing the calibration registers the calibration selection bits in the control register calslt1 and calslt0 determine which of the calibration registers are ad- dressed (see table iv). the addressing applies to both the read and write operations for the calibration registers. the user should not attempt to read from and write to the calibration registers at the same time. table iv. calibration register addressing calslt1 calslt0 comment 0 0 this combination addresses the gain (1) , offset (1) and dac registers (8) . ten registers in total. 0 1 this combination addresses the gain (1) and offset (1) registers. two registers in total. 1 0 this combination addresses the offset register . one register in total. 1 1 this combination addresses the gain register . one register in total. writing to/reading from the calibration registers for writing to the calibration registers a write to the control reg- ister is required to set the calslt0 and calslt1 bits. for reading from the calibration registers a write to the control reg- ister is required to set the calslt0 and calslt1 bits, but also to set the rdslt1 and rdslt0 bits to 10 (this addresses the calibration registers for reading). the calibration register pointer is reset on writing to the control register setting the calslt1 and calslt0 bits, or upon completion of all the calibration register write/read operations. when reset it points to the first calibration register in the selected write/read sequence. the calibration register pointer will point to the gain calibration register upon reset in all but one case, this case be- ing where the offset calibration register is selected on its own (calslt1 = 1, calslt0 = 0). where more than one cali- bration register is being accessed, the calibration register pointer will be automatically incremented after each calibration register write/read operation. the order in which the 10 calibra- tion registers are arranged is shown in figure 7. the user may abort at any time before all the calibration register write/read operations are completed, and the next control register write operation will reset the calibration register pointer. the flow- chart in figure 8 shows the sequence for writing to the calibra- tion registers and figure 9 for reading. cal register address pointer calibration registers gain register offset register dac 1st msb register dac 8th msb register (1) (2) (3) (10) calibration register address pointer position is determined by the number of calibration registers addressed and the number of read/write operations. figure 7. calibration register arrangement when reading from the calibration registers there will always be two leading zeros for each of the registers. when operating in serial interface mode 1, the read operations to the calibration registers cannot be aborted. the full number of read operations must be completed (see section on serial interface mode 1 tim- ing for more detail). start write to cal register (addr1 = 1, addr0 = 0) finished last register write operation or abort ? yes no cal register pointer is automatically reset write to control register setting stcal = 0 and calslt1, calslt0 = 00, 01, 10, 11 cal register pointer is automatically incremented figure 8. flowchart for writing to the calibration registers
C13C rev. a ad7851 finished last register write operation or abort ? yes no cal register pointer is automatically incremented read cal register cal register pointer is automatically reset write to control register setting stcal = 0, rdslt1 = 1, rdslt0 = 0, and calslt1, calslt0 = 00, 01, 10, 11 start figure 9. flowchart for reading from the calibration registers adjusting the offset calibration register the offset calibration register contains 16 bits, two leading zeros and 14 data bits. by changing the contents of the offset register, different amounts of offset on the analog input signal can be compensated for. increasing the number in the offset calibration register compensates for negative offset on the analog input sig- nal, and decreasing the number in the offset calibration register compensates for positive offset on the analog input signal. the default value of the offset calibration register is 0010 0000 0000 0000 approximately. this is not an exact value, but the value in the offset register should be close to this value. each of the 14 data bits in the offset register is binary weighted; the msb has a weighting of 5% of the reference voltage, the msb-1 has a weighting of 2.5%, the msb-2 has a weighting of 1.25%, and so on down to the lsb which has a weighting of 0.0006%. this gives a resolution of 0.0006% of v ref approximately. more accurately the resolution is (0.05 v ref )/2 13 volts = 0.015 mv, with a 2.5 v reference. the maximum offset that can be compensated for is 5% of the reference voltage, which equates to 125 mv with a 2.5 v reference and 250 mv with a 5 v reference. q. if a +20 mv offset is present in the analog input signal and the reference voltage is 2.5 v, what code needs to be written to the offset register to compensate for the offset? a. 2.5 v reference implies that the resolution in the offset reg- ister is 5% 2.5 v/2 13 = 0.015 mv. +20 mv/0.015 mv = 1310.72; rounding to the nearest number gives 1311. in binary terms this is 0101 0001 1111, therefore decrease the offset register by 0101 0001 1111. this method of compensating for offset in the analog input sig- nal allows for fine tuning the offset compensation. if the offset on the analog input signal is known, there will be no need to apply the offset voltage to the analog input pins and do a system calibration. the offset compensation can take place in software. adjusting the gain calibration register the gain calibration register contains 16 bits, two leading 0s and 14 data bits. the data bits are binary weighted as in the off- set calibration register. the gain register value is effectively mul- tiplied by the analog input to scale the conversion result over the full range. increasing the gain register compensates for a smaller analog input range and decreasing the gain register com- pensates for a larger input range. the maximum analog input range that the gain register can compensate for is 1.025 times the reference voltage, and the minimum input range is 0.975 times the reference voltage.
ad7851 C14C rev. a circuit information the ad7851 is a fast, 14-bit single supply a/d converter. the part requires an external 6/7 mhz master clock (clkin), two c ref capacitors, a convst signal to start conversion and power supply decoupling capacitors. the part provides the user with track/hold, on-chip reference, calibration features, a/d converter and serial interface logic functions on a single chip. the a/d converter section of the ad7851 consists of a conven- tional successive-approximation converter based around a ca- pacitor dac. the ad7851 accepts an analog input range of 0 v to +v dd where the reference can be tied to v dd . the refer- ence input to the part is buffered onchip. a major advantage of the ad7851 is that a conversion can be initiated in software as well as applying a signal to the convst pin. another innovative feature of the ad7851 is self-calibration on power-up, which is initiated having a 0.01 m f capacitor from the cal pin to agnd, to give superior dc accuracy. the part should be allowed 150 ms after power-up to perform this auto- matic calibration before any reading or writing takes place. the part is available in a 24-pin ssop package and this offers the user considerable space saving advantages over alternative solutions. converter details the master clock for the part must be applied to the clkin pin. conversion is initiated on the ad7851 by pulsing the convst input or by writing to the control register and setting the convst bit to 1. on the rising edge of convst (or at the end of the control register write operation), the on-chip track/hold goes from track to hold mode. the falling edge of the clkin signal which follows the rising edge of the edge of convst signal initiates the conversion, provided the rising edge of convst occurs at least 10 ns typically before this clkin edge. the conversion cycle will take 18.5 clkin peri- ods from this clkin falling edge. if the 10 ns setup time is av dd dv dd ain(+) ain(? amode c ref1 c ref2 sleep din dout sync sm1 sm2 convst agnd dgnd clkin sclk ref in /ref out polarity ad7851 analog (5v) supply 0.01? 0.1? 10? dv dd unipolar range 0.01? 47nf serial mode selection bits master clock input conversion start input frame sync output serial data output 0.01? cal auto cal on power-up internal reference 0v to v ref input 7mhz/6mhz oscillator serial clock output dv dd 333khz/285khz pulse generator optional external reference ad1584/ref198 0.01? analog (5v) supply 0.1? 10? din at dgnd => no writing to device 0.01? 470nf ch1 ch2 ch3 ch4 oscilloscope 2 leading zeros for adc data figure 10. typical circuit not met, the conversion will take 19.5 clkin periods. the maximum specified conversion time is 3.25 m s (6 mhz ) and 2.8 m s (7 mhz) for the a and k grades respectively for the ad7851 (19.5 t clkin, clkin = 6/7 mhz). when a conversion is completed, the busy output goes low, and then the result of the conversion can be read by accessing the data through the se- rial interface. to obtain optimum performance from the part, the read operation should not occur during the conversion or 500 ns prior to the next convst rising edge. however, the maximum throughput rates are achieved by reading/writing dur- ing conversion, and reading/writing during conversion is likely to degrade the signal to (noise + distortion) by only 0.5 dbs. the ad7851 can operate at throughput rates up to 333 khz. for the ad7851 a conversion takes 19.5 clkin periods, 2 clkin periods are needed for the acquisition time giving a full cycle time of 3.59 m s (= 279 khz, clkin = 6 mhz) for the k grade and 3.08 m s (= 325 khz, clkin = 7 mhz) for the a grade. typical connection diagram figure 10 shows a typical connection diagram for the ad7851. the din line is tied to dgnd so that no data is written to the part. the agnd and the dgnd pins are connected together at the device for good noise suppression. the cal pin has a 0.01 m f capacitor to enable an automatic self-calibration on power-up. the sclk and sync are configured as outputs by having sm1 and sm2 at dv dd . the conversion result is output in a 16-bit word with 2 leading zeros followed by the msb of the 14-bit result. note that after the av dd and dv dd power-up, the part will require 150 ms for the internal reference to settle and for the automatic calibration on power-up to be completed. for applications where power consumption is a major concern, the sleep pin can be connected to dgnd. see power-down section for more detail on low power applications.
C15C rev. a ad7851 analog input the equivalent circuit of the analog input section is shown in figure 11. during the acquisition interval the switches are both in the track position and the ain(+) charges the 20 pf capacitor through the 125 w resistance. on the rising edge of convst switches sw1 and sw2 go into the hold position retaining charge on the 20 pf capacitor as a sample of the signal on ain(+). the ain(C) is connected to the 20 pf capacitor, and this unbalances the voltage at node a at the input of the comparator. the capacitor dac adjusts during the remainder of the conversion cycle to restore the voltage at node a to the cor- rect value. this action transfers a charge, representing the analog input signal, to the capacitor dac which in turn forms a digital representation of the analog input signal. the voltage on the ain(C) pin directly influences the charge transferred to the capacitor dac at the hold instant. if this voltage changes during the conversion period, the dac representation of the analog input voltage will be altered. therefore it is most important that the voltage on the ain(C) pin remains constant during the con- version period. furthermore, it is recommended that the ain(C) pin is always connected to agnd or to a fixed dc voltage. capacitor dac comparator hold track sw2 node a 20pf sw1 track hold 125 w 125 w ain(+) ain(? c ref2 figure 11. analog input equivalent circuit acquisition time the track and hold amplifier enters its tracking mode on the fall- ing edge of the busy signal. the time required for the track and hold amplifier to acquire an input signal will depend on how quickly the 20 pf input capacitance is charged. the acquisition time is calculated using the formula: t acq = 9 (r in + 125 w ) 20 pf where r in is the source impedance of the input signal, and 125 w , 20 pf is the input r, c. dc/ac applications for dc applications high source impedances are acceptable, pro- vided there is enough acquisition time between conversions to charge the 20 pf capacitor. the acquisition time can be calcu- lated from the above formula for different source impedances. for example with r in = 5 k w , the required acquisition time will be 922 ns. for ac applications, removing high frequency components from the analog input signal is recommended by use of an rc low- pass filter on the ain(+) pin, as shown in figure 13. in applica- tions where harmonic distortion and signal to noise ratio are critical, the analog input should be driven from a low impedance source. large source impedances will significantly affect the ac performance of the adc. this may necessitate the use of an in- put buffer amplifier. the choice of the op amp will be a function of the particular application. when no amplifier is used to drive the analog input the source impedance should be limited to low values. the maximum source impedance will depend on the amount of total harmonic distortion (thd) that can be tolerated. the thd will increase as the source impedance increases and performance will degrade. figure 12 shows a graph of the total harmonic distortion vs. analog input signal frequency for different source impedances. with the setup as in figure 13, the thd is at the C90 db level. with a source impedance of 1 k w and no capacitor on the ain(+) pin, the thd increases with frequency. thd ?db input frequency ?khz ?0 ?0 ?10 ?00 ?0 ?0 ?0 1 166 10 20 50 80 thd vs. frequency for different source impedances r in = 560 w r in = 10 w , 10nf as in figure 13 140 120 100 figure 12. thd vs. analog input frequency in a single supply application (5 v), the v+ and vC of the op amp can be taken directly from the supplies to the ad7851 which eliminates the need for extra external power supplies. when operating with rail-to-rail inputs and outputs at frequen- cies greater than 10 khz, care must be taken in selecting the particular op amp for the application. in particular, for single supply applications the input amplifiers should be connected in a gain of C1 arrangement to get the optimum performance. fig- ure 13 shows the arrangement for a single supply application with a 10 w and 10 nf low-pass filter (cutoff frequency 320 khz) on the ain(+) pin. note that the 10 nf is a capacitor with good linearity to ensure good ac performance. recommended single supply op amp is the ad820. ic1 +5v 10k w 10k w 10k w v+ v 10k w 10 w ad820 v in ? ref /2 to +v ref /2 v ref /2 10? 0.1? 10nf (npo) to ain(+) of ad7851 figure 13. analog input buffering
ad7851 C16C rev. a 4.096 v/16384 = 0.25 mv when v ref = 4.096 v. the ideal in- put/output transfer characteristic for the unipolar range is shown in figure 16. +fs ?lsb output code 0v 111...111 111...110 111...101 111...100 000...011 000...001 000...000 000...010 v in = (ain(+) ?ain(?), input voltage 1lsb 1lsb = fs 16384 figure 16. ad7851 unipolar transfer characteristic figure 15 shows the ad7851s v ref /2 bipolar analog input configuration (where ain(+) cannot go below 0 v so for the full bipolar range then the ain(C) pin should be biased to +v ref /2). once again the designed code transitions occur midway between successive integer lsb values. the output coding is 2s comple- ment with 1 lsb = 16384 = 4.096 v/16384 = 0.25 mv. the ideal input/output transfer characteristic is shown in figure 17. ?1 lsb fs = v ref v 1lsb = fs 16384 output code v ref /2 011...111 011...110 000...001 000...000 100...001 100...000 100...010 v in = (ain(+) ?ain(?), input voltage 0v + fs 111...111 (v ref /2) ? lsb (v ref /2) +1 lsb figure 17. ad7851 bipolar transfer characteristic input ranges the analog input range for the ad7851 is 0 v to v ref in both the unipolar and bipolar ranges. the only difference between the unipolar range and the bipolar range is that in the bipolar range the ain(C) has to be biased up to +v ref /2 and the output coding is 2s complement (see table v and figures 14 and 15). the unipolar or bipolar mode is se- lected by the amode pin (0 for the unipolar range and 1 for the bipolar range). table v. analog input connections analog input input connections connection range ain(+) ain(C) diagram amode 0 v to v ref 1 v in agnd figure 8 dgnd v ref /2 2 v in v ref /2 figure 9 dv dd notes 1 output code format is straight binary. 2 range is v ref /2 biased about v ref /2. output code format is 2s complement. note that the ain(C) pin on the ad7851 can be biased up above agnd in the unipolar mode also, if required. the ad- vantage of biasing the lower end of the analog input range away from agnd is that the user does not have to have the analog input swing all the way down to agnd. this has the advantage in true single supply applications that the input amplifier does not have to swing all the way down to agnd. the upper end of the analog input range is shifted up by the same amount. care must be taken so that the bias applied does not shift the upper end of the analog input above the av dd supply. in the case where the reference is the supply, av dd , the ain(C) must be tied to agnd in unipolar mode. ain(+) ain(? amode ad7851 unipolar analog input range selected dout straight binary format v in = 0 to v ref track and hold amplifier figure 14. 0 v to v ref unipolar input configuration transfer functions for the unipolar range the designed code transitions occur mid- way between successive integer lsb values (i.e., 1/2 lsb, 3/2 lsbs, 5/2 lsbs . . . fs C3/2 lsbs). the output coding is straight binary for the unipolar range with 1 lsb = fs/16384 = 2s complement format v ref /2 dv dd ain(+) ain(? amode ad7851 unipolar analog input range selected dout v in = 0 to v ref track and hold amplifier figure 15. v ref /2 about v ref /2 bipolar input configuration
C17C rev. a ad7851 reference section for specified performance, it is recommended that when using an external reference this reference should be between 4 v and the analog supply av dd . the connections for the relevant refer- ence pins are shown in the typical connection diagrams. if the internal reference is being used, the ref in /ref out pin should have a 100 nf capacitor connected to agnd very close to the ref in /ref out pin. these connections are shown in figure 18. if the internal reference is required for use external to the adc, it should be buffered at the ref in /ref out pin and a 100 nf connected from this pin to agnd. the typical noise performance for the internal reference, with 5 v supplies is 150 nv/ ? hz @ 1 khz and dc noise is 100 m v p-p. ref in /ref out ad7851 analog supply +5v av dd dv dd 0.01? 0.1? 10? c ref1 c ref2 0.01? 47nf 0.01? 470nf 0.1? 10 w figure 18. relevant connections when using internal reference the other option is that the ref in /ref out pin be overdriven by connecting it to an external reference. this is possible due to the series resistance from the ref in /ref out pin to the internal reference. this external reference can have a range that includes av dd . when using av dd as the reference source, the 100 nf capacitor from the ref in /ref out pin to agnd should be as close as possible to the ref in /ref out pin, and also the c ref1 pin should be connected to av dd to keep this pin at the same level as the reference. the connections for this arrangement are shown in figure 19. when using av dd it may be necessary to add a resistor in series with the av dd supply. this will have the effect of filtering the noise associated with the av dd supply. ref in /ref out ad7851 analog supply +5v av dd dv dd 0.01? 0.1? 10? c ref1 c ref2 0.01? 47nf 0.01? 470nf 0.1? 10 w 10 w figure 19. relevant connections when using av dd as the reference ad7851 performance curves figure 20 shows a typical fft plot for the ad7851 at 333 khz sample rate and 10 khz input frequency. frequency ?khz 0 ?0 ?20 0 100 20 snr ?db 40 60 80 ?0 ?0 ?0 ?00 av dd = dv dd = 5v f sample = 333 khz f in = 10khz snr = 79.5db thd = ?5.2 figure 20. fft plot figure 21 shows the snr versus frequency for 5 v supply and a 4.096 external references (5 v reference is typically 1 db bet- ter performance). input frequency ?khz 79 75 0 166 20 50 120 140 78 77 76 s(n+d) ratio ?db 10 80 100 figure 21. snr vs. frequency figure 22 shows the power supply rejection ratio versus frequency for the part. the power supply rejection ratio is defined as the ratio of the power in adc output at frequency f to the power of a full-scale sine wave. psrr (db) = 10 log (pf/pfs) pf = power at frequency f in adc output, pfs = power of a full- scale sine wave. here a 100 mv peak-to-peak sine wave is coupled onto the av dd supply while the digital supply is left unaltered.
ad7851 C18C rev. a input frequency ?khz ?2 ?4 ?0 0.91 100 13.4 25.7 38.3 50.3 ?6 ?8 ?0 ?8 psrr ?db ?2 ?4 ?6 63.5 74.8 87.4 av dd = dv dd = 5.0v 100mv pk-pk sinewave on av dd ref in = 4.098 ext reference figure 22. psrr vs. frequency power-down options the ad7851 provides flexible power management to allow the user to achieve the best power performance for a given through- put rate. the power management options are selected by pro- gramming the power management bits, pmgt1 and pmgt0, in the control register and by use of the sleep pin. table vi summarizes the power-down options that are available and how they can be selected by using either software, hardware or a combination of both. the ad7851 can be fully or partially pow- ered down. when fully powered down, all the on-chip circuitry is powered down and i dd is 1 m a typ. if a partial power-down is selected, then all the on-chip circuitry except the reference is powered down and i dd is 400 m a typ. the choice of full or par- tial power-down does not give any sig nificant improvement in throughput with a power-down between conversions. this is dis- cussed in the next section power-up times . but a partial power-down does allow the on-chip reference to be used exter- nally even though the rest of the ad7851 circuitry is powered down. it also allows the ad7851 to be powered up faster after a long power-down period when using the on-chip reference (see power-up times using on-chip reference ). when using the sleep pin, the power management bits pmgt1 and pmgt0 should be set to zero (default status on power-up). bringing the sleep pin logic high ensures normal operation, and the part does not power down at any stage. this may be necessary if the part is being used at high throughput rates when it is not possible to power down between conver- sions. if the user wishes to power down between conversions at lower throughput rates (i.e., <100 ksps for the ad7851) to achieve better power performances, then the sleep pin should be tied logic low. if the power-down options are to be selected in software only, then the sleep pin should be tied logic high. by setting the power management bits pmgt1 and pmgt0 as shown in table vi, a full power-down, full power-up, full power- down between conversions, and a partial power-down between conversions can be selected. a combination of hardware and software selection can also be used to achieve the desired effect. table vi. power management options pmgt1 pmgt0 sleep bit bit pin comment 0 0 0 full power-down between conversions (hw/sw) 0 0 1 full power-up (hw/sw) 0 1 x full power-down between conversions (sw) 1 0 x full power-down (sw) 1 1 x partial power-down between conversions (sw) note sw = software selection, hw = hardware selection. 0v to v ref input din at dgnd => no writing to device 3-wire mode selected current, i = 12ma typ av dd dv dd ain(+) ain(? amode c ref1 c ref2 sleep din dout sync sm1 sm2 convst agnd dgnd clkin sclk ref in /ref out polarity ad7851 analog (+5v) supply 0.01? 0.1? 10? dv dd unipolar range 0.01? 47nf serial mode selection bits master clock input conversion start input serial data output 0.01? cal internal reference 6/7mhz oscillator serial clock output 285/ 333khz pulse generator optional external reference 0.01? 0.01? 470nf auto cal on power-up ref198 auto power- down after conversion low power ?/? figure 23. typical low power circuit
C19C rev. a ad7851 power-up times using an external reference when the ad7851 are powered up, the parts are powered up from one of two conditions. first, when the power supplies are initially powered up and, secondly, when the parts are powered up from either a hardware or software power-down (see last section). when av dd and dv dd are powered up, the ad7851 enters a mode whereby the convst signal initiates a timeout followed by a self-calibration. the total time taken for this time-out and calibration is approximately 35 mssee calibration on power-up in the calibration section of this data sheet. during power-up the functionality of the sleep pin is disabled, i.e., the part will not power down until the end of the calibration if sleep is tied logic low. the power-up calibration mode can be disabled if the user writes to the control register before a convst signal is applied. if the time out and self-calibration are disabled, then the user must take into account the time required by the ad7851 to power up before a self-calibration is carried out. this power-up time is the time taken for the ad7851 to power up when power is first applied (300 m s typ) or the time it takes the external reference to settle to the 14-bit levelwhichever is the longer. the ad7851 powers up from a full hardware or software power-down in 5 m s typ. this limits the throughput which the part is capable of to 120 ksps for the k grade and 126 ksps for the a grade when powering down between conversions. fig- ure 24 shows how power-down between conversions is imple- mented using the convst pin. the user first selects the power-down between conversions option by using the sleep pin and the power management bits, pmgt1 and pmgt0, in the control register. see last section. in this mode the ad7851 automatically enters a full power-down at the end of a conver- sion, i.e., when busy goes low. the falling edge of the next convst pulse causes the part to power up. assuming the ex- ternal reference is left powered up, the ad7851 should be ready for normal operation 5 m s after this falling edge. the rising edge of convst initiates a conversion so the convst pulse should be at least 5 m s wide. the part automatically powers down on completion of the conversion. where the software con- vert start is used, the part may be powered up in software before a conversion is initiated. 5? 3.25? t convert power-up time normal operation full power-down power-up time start conversion on rising edge power-up on falling edge convst busy figure 24. using the convst pin to power up the ad7851 for a conversion using the internal (on-chip) reference as in the case of an external reference, the ad7851 can power up from one of two conditions, power-up after the supplies are connected or power-up from hardware/software power-down. when using the on-chip reference and powering up when av dd and dv dd are first connected, it is recommended that the power-up calibration mode be disabled as explained above. when using the on-chip reference, the power-up time is effec- tively the time it takes to charge up the external capacitor on the ref in /ref out pin. this time is given by the equation: t up = 9 r c where r ? 150k and c = external capacitor. the recommended value of the external capacitor is 100 nf; this gives a power-up time of approximately 135 ms before a calibration is initiated and normal operation should commence. when c ref is fully charged, the power-up time from a hardware or software power-down reduces to 5 m s. this is because an internal switch opens to provide a high impedance discharge path for the reference capacitor during power-downsee figure 25. an added advantage of the low charge leakage from the reference capacitor during power-down is that even though the reference is being powered down between conversions, the refer- ence capacitor holds the reference voltage to within 0.5 lsbs with throughput rates of 100 samples/second and over with a full power-down between conversions. a high input impedance op amp like the ad707 should be used to buffer this reference capacitor if it is being used externally. note, if the ad7851 is left in its powered-down state for more than 100 ms, the charge on c ref will start to leak away and the power-up time will increase. if this long power-up time is a problem, the user can use a partial power-down for the last conversion so the reference remains powered up. ad7851 ref in /ref out external capacitor switch opens during power-down buf on-chip reference to other circuitry figure 25. on-chip reference during power-down power vs. throughput rate the main advantage of a full power-down after a conversion is that it significantly reduces the power consumption of the part at lower throughput rates. when using this mode of operation, the ad7851 is only powered up for the duration of the conver- sion. if the power-up time of the ad7851 is taken to be 5 m s and it is assumed that the current during power up is 12 ma typ, then power consumption as a function of throughput can easily be calculated. the ad7851 has a conversion time of 3.25 m s with a 6 mhz external clock. this means the ad7851 consumes 12 ma typ for 8.25 m s in every conversion cycle if the parts are powered down at the end of a conversion. the graph, figure 26, shows the power consumption of the ad7851 as a function of through put. table vii lists the power consump- tion for various throughput rates.
ad7851 C20C rev. a table vii. power consumption vs. throughput power throughput rate ad7851 1 ksps 9 mw 2 ksps 18 mw throughput rate ?hz 100 10 0.01 0 2000 200 1 400 600 800 1000 1200 1400 1600 1800 0.1 power ?mw figure 26. power vs. throughput ad7851 note when setting the power-down mode by writing to the part, it is recommended to be operating in an interface mode other than interface modes 4, and 5. this way the user has more control to initiate power-down, and power-up commands. calibration section calibration overview the automatic calibration that is performed on power-up en- sures that the calibration options covered in this section will not be required in a significant amount of applications. the user will not have to initiate a calibration unless the operating condi- tions change (clkin frequency, analog input mode, reference voltage, temperature, and supply voltages). the ad7851 have a number of calibration features that may be required in some ap- plications and there are a number of advantages in performing these different types of calibration. first, the internal errors in the adc can be reduced significantly to give superior dc perfor- mance; and se cond, system offset and gain errors can be removed. this allows the user to remove reference errors (whether it be internal or external reference) and to make use of the full dy- namic range of the ad7851 by adjusting the analog input range of the part for a specific system. there are two main calibration modes on the ad7851, self-cali- bration and system calibration. there are various options in both self-calibration and system calibration as outlined previ- ously in table iii. all the calibration functions can be initiated by pulsing the cal pin or by writing to the control register and setting the stcal bit to 1. the timing diagrams that follow in- volve using the cal pin. the duration of each of the different types of calibrations is given in table viii for the ad7851 with a 6 mhz/7 mhz mas- ter clock. these calibration times are master clock dependent. table viii. calibration times (ad7851 with 6 mhz clkin) type of self- or system calibration time full 41.7 ms gain + offset 9.26 ms offset 4.63 ms gain 4.63 ms automatic calibration on power-on the cal pin has a 0.15 m a pull-up current source connected to it internally to allow for an automatic full self-calibration on power-on. a full self-calibration will be initiated on power-on if a 10 nf capacitor is connected from the cal pin to agnd. the internal current source connected to the cal pin charges up the external capacitor and the time required to charge the ex- ternal capacitor will be 100 ms approximately. this time is large enough to ensure that the internal reference is settled before the calibration is performed. however, if an external reference is be- ing used, this reference must have stabilized before the auto- matic calibration is initiated (if larger time than 100 ms is required then a larger capacitor on the cal pin should be used). after this 100 ms has elapsed, the calibration will be per- formed which will take 42 ms/36 ms (6 mhz /7 mhz clkin). therefore 142 ms/136 ms should be allowed before operating the part. after calibration, the part is accurate to the 14-bit level and the specifications quoted on the data sheet apply. there will be no need to perform another calibration unless the operating conditions change or unless a system calibration is required. self-calibration description there are a four different calibration options within the self- calibration mode. there is a full self-calibration where the dac, internal offset, and internal gain errors are calibrated out. then, there is the (gain + offset) self-calibration which cali- brates out the internal gain error and then the internal offset er- rors. the internal dac is not calibrated here. finally, there are the self-offset and self-gain calibrations which calibrate out the internal offset errors and the internal gain errors respectively. the internal capacitor dac is calibrated by trimming each of the capacitors in the dac. it is the ratio of these capacitors to each other that is critical, and so the calibration algorithm en- sures that this ratio is at a specific value by the end of the cali- bration routine. for the offset and gain there are two separate capacitors, one of which is trimmed when an offset or gain cali- bration is performed. again it is the ratio of these capacitors to the capacitors in the dac that is critical and the calibration al- gorithm ensures that this ratio is at a specified value for both the offset and gain calibrations. in bipolar mode the midscale error is adjusted for an offset calibration and the positive full-scale error is adjusted for the gain calibration; in unipolar mode the zero-scale error is ad- justed for an offset calibration and the positive full-scale error is adjusted for a gain calibration.
C21C rev. a ad7851 system offset calibration sys offset v ref ?1lsb agnd max system offset is 5% of v ref max system full scale is 2.5% from v ref analog input range v ref ?1lsb analog input range sys offset agnd max system offset is 5% of v ref v ref + sys offset figure 28. system offset calibration figure 29 shows a system gain calibration (assuming a system full scale greater than the reference voltage) where the analog input range has been increased after the system gain calibration is completed. a system full-scale voltage less than the reference voltage may also be accounted for a by a system gain calibration. system gain calibration v ref ?1lsb agnd max system full scale is 2.5% from v ref analog input range v ref ?1lsb analog input range agnd sys full s. sys full s. max system full scale is 2.5% from v ref figure 29. system gain calibration finally in figure 30 both the system offset and gain are accounted for by the system offset followed by a system gain calibration. first the analog input range is shifted upwards by the positive system offset and then the analog input range is adjusted at the top end to account for the system full scale. system offset calibration followed by system gain calibration sys offset v ref ?1lsb agnd max system offset is 5% of v ref max system full scale is 2.5% from v ref analog input range v ref ?1lsb analog input range sys offset agnd max system offset is 5% of v ref v ref + sys offset sys f.s. max system full scale is 2.5% from v ref sys f.s. figure 30. system (gain + offset) calibration self-calibration timing the diagram of figure 27 shows the timing for a full self- calibration. here the busy line stays high for the full length of the self-calibration. a self-calibration is initiated by bringing the cal pin low (which initiates an internal reset) and then high again or by writing to the control register and setting the stcal bit to 1 ( note that if the part is in a power-down mode, the cal pulse width must take account of the power-up time ). the busy line is triggered high from the rising edge of cal (or the end of the write to the control register if calibration is initiated in software), and busy will go low when the full self-calibration is complete after a time t cal as shown in figure 27. t 1 = 100ns min, t 15 = 2.5 t clkin max, t cal = 250026 t clkin cal (i/p) busy (o/p) t 1 t 15 t cal figure 27. timing diagram for full self-calibration for the self-(gain + offset), self-offset and self-gain calibrations, the busy line will be triggered high by the rising edge of the cal signal (or the end of the write to the control register if cali- bration is initiated in software) and will stay high for the full du- ration of the self-calibration. the length of time that the busy is high for will depend on the type of self-calibration that is initi- ated. typical figures are given in table ix. the timing dia- grams for the other self-calibration options will be similar to that outlined in figure 27. system calibration description system calibration allows the user to take out system errors external to the ad7851 as well as calibrate the errors of the ad7851 itself. the maximum calibration range for the system offset errors is 5% of v ref and for the system gain errors is 2.5% of v ref . this means that the maximum allowable system offset voltage applied between the ain(+) and ain(C) pins for the calibration to adjust out this error is 0.05 v ref ( i.e., the ain(+) can be 0.05 v ref above ain(C) or 0.05 v ref below ain(C) ). for the system gain error the maximum allowable system full-scale voltage, in unipolar mode, that can be applied between ain(+) and ain(C) for the calibration to adjust out this error is v ref 0.025 v ref ( i.e. , the ain(+) can be v ref + 0.025 v ref above ain(C) or v ref C 0.025 v ref above ain(C) ). if the system offset or system gain errors are outside the ranges mentioned, the system calibration algorithm will reduce the errors as much as the trim range allows. figures 28 through 30 illustrate why a specific type of system calibration might be used. figure 29 shows a system offset cali- bration (assuming a positive offset) where the analog input range has been shifted upwards by the system offset after the system offset calibration is completed. a negative offset may also be accounted for by a system offset calibration.
ad7851 C22C rev. a system gain and offset interaction the inherent architecture of the ad7851 leads to an interaction between the system offset and gain errors when a system calibra- tion is performed. therefore it is recommended to perform the cycle of a system offset calibration followed by a system gain calibration twice. separate system offset and system gain cali- brations reduce the offset and gain errors to at least the 14-bit level. by performing a system offset calibration first and a sys- tem gain calibration second, priority is given to reducing the gain error to zero before reducing the offset error to zero. if the system errors are small, a system offset calibration would be per- formed, followed by a system gain calibration. if the systems er- rors are large (close to the specified limits of the calibration range), this cycle would be repeated twice to ensure that the off- set and gain errors were reduced to at least the 14-bit level. the advantage of doing separate system offset and system gain cali- brations is that the user has more control over when the analog inputs need to be at the required levels, and the convst sig- nal does not have to be used. alternatively, a system (gain + offset) calibration can be per- formed. it is recommended to perform three system (gain + off- set) calibrations to reduce the offset and gain errors to the 14-bit level. for the system (gain + offset) calibration priority is given to reducing the offset error to zero before reducing the gain er- ror to zero. thus if the system errors are small then two system (gain + offset) calibrations will be sufficient. if the system errors are large (close to the specified limits of the calibration range), three system (gain + offset) calibrations may be required to re- duced the offset and gain errors to at least the 14-bit level. there will never be any need to perform more than three system (offset + gain) calibrations. in bipolar mode the midscale error is adjusted for an offset cali- bration and the positive full-scale error is adjusted for the gain calibration; in unipolar mode the zero-scale error is adjusted for an offset calibration and the positive full-scale error is ad- justed for a gain calibration. system calibration timing the calibration timing diagram in figure 31 is for a full system calibration where the falling edge of cal initiates an internal reset before starting a calibration ( note that if the part is in power- down mode the cal pulse width must take account of the power-up time) . if a full system calibration is to be performed in software, it is easier to perform separate gain and offset calibrations so that the convst bit in the control register does not have to be programmed in the middle of the system calibration sequence. the rising edge of cal starts calibration of the internal dac and causes the busy line to go high. if the control register is set for a full system calibration, the convst must be used also. the full-scale system voltage should be applied to the ana- log input pins from the start of calibration. the busy line will go low once the dac and system gain calibration are complete. next the system offset voltage is applied to the ain pin for a minimum setup time (t setup ) of 100 ns before the rising edge of the convst and remain until the busy signal goes low. the rising edge of the convst starts the system offset calibration section of the full system calibration and also causes the busy signal to go high. the busy signal will go low after a time t cal2 when the calibration sequence is complete. the timing for a system (gain + offset) calibration is very similar to that of figure 31, the only difference being that the time t cal1 will be replaced by a shorter time of the order of t cal2 as the internal dac will not be calibrated. the busy signal will signify when the gain calibration is finished and when the part is ready for the offset calibration. convst (i/p) ain (i/p) t 16 t setup cal (i/p) busy (o/p) t 1 t 15 t cal1 t cal2 v system full scale v offset t 1 = 100ns min, t 14 = 50 max, t 15 = 4 t clkin max, t cal1 = 222228 t clkin max, t cal2 = 27798 t clkin figure 31. timing diagram for full system calibration the timing diagram for a system offset or system gain calibra- tion is shown in figure 32. here again the cal is pulsed and the rising edge of the cal initiates the calibration sequence (or the calibration can be initiated in software by writing to the con- trol register). the rising edge of the cal causes the busy line to go high and it will stay high until the calibration sequence is finished. the analog input should be set at the correct level for a minimum setup time (t setup ) of 100 ns before the rising edge of cal and stay at the correct level until the busy signal goes low. ain (i/p) t setup cal (i/p) busy (o/p) t 15 t cal2 t 1 v system full scale or v system offset figure 32. timing diagram for system gain or system offset calibration
C23C rev. a ad7851 serial interface summary table ix details the five interface modes and the serial clock edges from which the data is clocked out by the ad7851 (dout edge) and that the data is latched in on (din edge). the logic level of the polarity pin is shown and it is clear that this reverses the edges. in interface modes 4 and 5 the sync always clocks out the first data bit and sclk will clock out the subsequent bits. in interface modes 1, 2, and 3 the sync is gated with the sclk and the polarity pin. thus the sync may clock out the msb of data. subsequent bits will be clocked out by the se- rial clock, sclk. the conditions for the sync clocking out the msb of data is as follows: with the polarity pin high the falling edge of sync will clock out the msb if the serial clock is low when the sync goes low. with the polarity pin low the falling edge of sync will clock out the msb if the serial clock is high when the sync goes low. table ix. sclk active edge for different interface modes interface polarity dout din mode pin edge edge 1, 2, 3 0 sclk - sclk 1 sclk sclk - 4, 5 0 sclk sclk - 1 sclk - sclk resetting the serial interface when writing to the part via the din line there is the possibility of writing data into the incorrect registers, such as the test regis- ter for instance, or writing the incorrect data and corrupting the serial interface. the sync pin acts as a reset. bringing the sync pin high resets the internal shift register. the first data bit after the next sync falling edge will now be the first bit of a new 16-bit transfer. it is also possible that the test register con- tents were altered when the interface was lost. therefore, once the serial interface is reset, it may be necessary to write the 16- bit word 0100 0000 0000 0010 to restore the test register to its default value. now the part and serial interface are completely reset. it is always useful to retain the ability to program the sync line from a port of the m controller/dsp to have the abil- ity to reset the serial interface. table x summarizes the interface modes provided by the ad7851. it also outlines the various m p/ m c to which the par- ticular interface is suited. the interface mode is determined by the serial mode selection pins sm1 and sm2. interface mode 2 is the default mode. note that interface mode 1 and 2 have the same combination of sm1 and sm2. interface mode 1 may only be set by programming the control register (see section on control register). external sclk and sync signals ( sync may be hardwired low) are required for interfaces modes 1, 2, and 3. in interface modes 4 and 5 the ad7851 generates the sclk and sync . some of the more popular m processors, m controllers, and the dsp machines that the ad7851 will interface to directly are mentioned here. this does not cover all m cs, m ps and dsps. the interface mode of the ad7851 that is mentioned here for a specific m c, m p, or dsp is only a guide and in most cases an- other interface mode may work just as well. a more detailed timing description on each of the interface modes follows. table x. interface mode description sm1 sm2 m processor/ interface pin pin m controller mode 0 0 8xc51 1 (2-wire) 8xl51 (din is an input/ pic17c42 output pin) 0 0 68hc11 2 (3-wire, spi/qspi) 68l11 (default mode) 0 1 68hc16 3 (qspi) pic16c64 (external serial adsp-21xx clock, sclk, and dsp56000 external frame sync, dsp56001 sync , are required) dsp56002 dsp56l002 tms320c30 1 0 68hc16 4 (dsp is slave) (ad7851 generates a noncontinuous (16 clocks) serial clock, sclk, and the frame sync, sync ) 1 1 adsp-21xx 5 (dsp is slave) dsp56000 (ad7851 dsp56001 generates a dsp56002 continuous serial dsp56l002 clock, sclk, and the tms320c20 frame sync, sync ) tms320c25 tms320c30 tms320c5x tms320lc5x
ad7851 C24C rev. a db15 db0 db0 db15 t 3 din (i/o) t 3 t 11 t 6 116 16 1 t 5a t 12 din becomes an input 3-state t 6 t 11 din becomes an output t 3 = ?.4 t sclk min (noncontinuous sclk) ?+0.4 t sclk min/max (continuous sclk), t 6 = 45 max, t 7 = 30ns min, t 8 = 20 min polarity pin logic high sync (i/p) sclk (i/p) t 8 t 14 t 7 data write data read figure 33. timing diagram for read/write operation with din as an input/output (i.e., interface mode 1, sm1 = sm2 = 0) db15 db0 db0 db15 din (i/o) t 6 = 45 max, t 7 = 30ns min, t 8 = 20 min, t 13 = 90 max, t 14 = 50ns max 6 116 16 1 t 13 t 6 din becomes an input t 6 polarity pin logic high sclk (i/p) t 8 t 14 t 7 data write data read figure 34. timing diagram for read/write operation with din as an input/output and sync input tied low (i.e., interface mode 1, sm1 = sm2 = 0) detailed timing section mode 1 (2-wire 8051 interface) the read and writing takes place on the din line and the con- version is initiated by pulsing the convst pin (note that in every write cycle the 2/ 3 mode bit must be set to 1). the con- version may be started by setting the convst bit in the con- trol register to 1 instead of using the convst line. below in figure 33 and in figure 34 are the timing diagrams for interface mode 1 in table xi where we are in the 2-wire inter- face mode. here the din pin is used for both input and output as shown. the sync input is level triggered active low and can be pulsed (figure 33) or can be constantly low (figure 34). in figure 33 the part samples the input data on the rising edge of sclk. after the 16th rising edge of sclk the din is con- figured as an output. when the sync is taken high the din is 3-stated. taking sync low disables the 3-state on the din pin and the first sclk falling edge clocks out the first data bit. once the 16 clocks have been provided the din pin will auto- matically revert back to an input after a time t 14 . note that a continuous sclk shown by the dotted waveform in figure 33 can be used provided that the sync is low for only 16 clock pulses in each of the read and write cycles. the polarity pin may be used to change the sclk edge which the data is sampled on and clocked out on. in figure 34 the sync line is tied low permanently and this re- sults in a different timing arrangement. with sync tied low permanently the din pin will never be 3-stated. the 16th rising edge of sclk configures the din pin as an input or an output as shown in the diagram. here no more than 16 sclk pulses must occur for each of the read and write operations. if reading from and writing to the calibration registers in this in- terface mode, all the selected calibration registers must be read from or written to. the read and write operations cannot be aborted. when reading from the calibration registers, the din pin will remain as an output for the full duration of all the cali- bration register read operations. when writing to the calibration registers, the din pin will remain as an input for the full dura- tion of all the calibration register write operations.
C25C rev. a ad7851 mode 2 (3-wire spi/qspi interface mode) this is the default interface mode. in figure 35 below we have the timing diagram for interface mode 2 which is the spi/qspi interface mode. here the sync input is active low and may be pulsed or tied permanently low. if sync is permanently low 16 clock pulses must be applied to the sclk pin for the part to operate correctly, and with a pulsed sync input a continuous sclk may be applied pro- vided sync is low for only 16 sclk cycles. in figure 35 the sync going low disables the three-state on the dout pin. the first falling edge of the sclk after the sync going low clocks out the first leading zero on the dout pin. the dout pin is 3-stated again a time t 12 after the sync goes high. with the din pin the data input has to be set up a time t 7 before the sclk rising edge as the part samples the input data on the sclk rising edge in this case. the polarity pin may be used to change the sclk edge which the data is sampled on and clocked out on. if resetting the interface is required, the sync must be taken high and then low. db0 db10 3-state 3-state db12 db13 db14 db15 db11 db12 db0 db10 db11 db13 db14 db15 t 3 = ?.4 t clkin min (noncontinuous sclk) ?+0.4 t sclk min/max (continuous sclk), t 6 = 45 max, t 7 = 30ns min, t 8 = 20 min, t 11 = 30 min (noncontinuous sclk) , 30/0.4 t sclk = ns min/max (continuous sclk) polarity pin logic high sync (i/p) 16 2345 16 sclk (i/p) t 9 t 5 t 11 t 3 t 10 t 12 dout (o/p) t 8 din (i/p) t 6 t 7 t 8 t 6 figure 35. spi/qspi mode 2 timing diagram for read/write operation with din input, dout output and sync input (sm1 = sm2 = 0) t 3 = ?.4 t clkin min (noncontinuous sclk) ?+0.4 t sclk min/max (continuous sclk), t 6 = 45 max, t 7 = 30ns min, t 8 = 20 min, t 11 = 30 min db0 db10 3-state 3-state db12 db13 db14 db15 db11 db12 db0 db10 db11 db13 db14 db15 polarity pin logic high sync (i/p) 16 2345 16 sclk (i/p) t 9 t 5 t 11 t 3 t 10 t 12 dout (o/p) t 8 din (i/p) t 6 t 7 t 8 t 6 figure 36. qspi mode 3 timing diagram for read/write operation with sync input edge triggered (sm1 = 0, sm2 = 1) mode 3 (qspi interface mode) figure 36 shows the timing diagram for interface mode 3. in this mode the dsp is the master and the part is the slave. here the sync input is edge triggered from high to low, and the 16 clock pulses are counted from this edge. since the clock pulses are counted internally then the sync signal does not have to go high after the 16th sclk rising edge as shown by the dotted sync line in figure 36. thus a frame sync that gives a high pulse, of one sclk cycle minimum duration, at the beginning of the read/write operation may be used. the rising edge of sync enables the 3-state on the dout pin. the falling edge of sync disables the 3-state on the dout pin, and data is clocked out on the falling edge of sclk. once sync goes high, the 3-state on the dout pin is enabled. the data input is sampled on the rising edge of sclk and thus has to be valid a time t 7 before this rising edge. the polarity pin may be used to change the sclk edge which the data is sampled on and clocked out on. if resetting the interface is required, the sync must be taken high and then low.
ad7851 C26C rev. a mode 4 and 5 (self-clocking modes) the timing diagrams in figure 38 and figure 39 are for inter- face modes 4 and 5. interface mode 4 has a noncontinuous sclk output and interface mode 5 has a continuous sclk output (sclk is switched off internally during calibration for both modes 4 and 5). these modes of operation are especially different to all the other modes since the sclk and sync are outputs. the sync is generated by the part as is the sclk. the master clock at the clkin pin is routed directly to the sclk pin for interface mode 5 (continuous sclk) and the clkin signal is gated with the sync to give the sclk (noncontinuous) for interface mode 4. the most important point about these two modes of operation mode is that the result of the current conversion is clocked out during the same conversion and a write to the part during this conversion is for the next conversion. the arrangement is shown in figure 37. figure 38 and figure 39 show more detailed timing for the arrangement of figure 37. write n+1 read n 3.25? write n+2 read n+1 write n+3 read n+2 the conversion result due to write n+1 is read here 3.25? 3.25? conversion n conversion n+1 conversion n+2 figure 37. in figure 38 the first point to note is that the busy, sync , and sclk are all outputs from the ad7851 with the convst being the only input signal. conversion is initiated with the convst signal going low. this convst falling edge also triggers the busy to go high. the convst signal rising edge triggers the sync to go low after a short delay (2.5 t clkin to 3.5 t clkin typically) after which the sclk will clock out the data on the dout pin during conversion. the data on the din pin is also clocked in to the ad7851 by the same sclk for the next conversion. the read/write operations must be complete after sixteen clock cycles ( which takes 3.25 m s approximately from the rising edge of convst assuming a 6 mhz clkin ). at this time the conversion will be complete, the sync will go high, and the busy will go low. the next falling edge of the convst must occur at least 330 ns after the falling edge of busy to allow the track/hold amplifier adequate acquisition time as shown in figure 38. this gives a throughput time of 3.68 m s. the maximum throughput rate in this case is 272 khz. t 1 convst (i/p) sclk (o/p) conversion ends 3.25? later serial read and write operations output serial shift register is reset read operation should end 500ns prior to next rising 400ns min busy (o/p) sync (o/p) conversion is initiated and track/hold goes into hold edge of convst t 1 = 100ns min t convert = 3.25? figure 38. mode 4, 5 timing diagram (sm1 = 1, sm2 = 1 and 0) in these interface modes the part is now the master and the dsp is the slave. figure 39 is an expansion of figure 38. the ad7851 will ensure sync goes low after the rising edge c of the continuous sclk (interface mode 5) in figure 39. only in the case of a noncontinuous sclk (interface mode 4) will the time t 4 apply. the first data bit is clocked out from the falling edge of sync . the sclk rising edge clocks out all subsequent bits on the dout pin. the input data present on the din pin is clocked in on the rising edge of the sclk. the polarity pin may be used to change the sclk edge which the data is sampled on and clocked out on. the sync will go high after the 16th sclk rising edge and before the rising edge d of the continuous sclk in figure 39. this ensures the part will not clock in an extra bit from the din pin or clock out an db12 db0 db10 db11 db13 db14 db15 db0 db10 db12 db13 db14 db15 db11 3-state 3-state polarity pin logic high sync (o/p) 16 2345 16 sclk (o/p) t 9 t 5 t 11a t 4 t 10 t 12 dout (o/p) t 8 din (i/p) t 4 = 0.6 t sclk (noncontinuous sclk), t 6 = 45ns max, t 7 = 30ns min, t 8 = 20ns min , t 11a = 50ns max t 6 t 7 t 8 d c figure 39. timing diagram for read/write with sync output and sclk output (continuous and noncontinuous) (i.e., operating mode numbers 4 and 5, sm1 = 1, sm2 = 1 and 0)
C27C rev. a ad7851 extra bit on the dout pin. if the user has control of the convst pin but does not want to exercise it for every conversion, the control register may be used to start a conversion. setting the convst bit in the control register to 1 starts a conversion. if the user does not have con- trol of the convst pin, a conversion should not initiated by writing to the control register. the reason for this is that the user may get locked out and not be able to perform any fur- ther write/read operations. when a conversion is started by writ- ing to the control register, the sync goes low and read/write operations take place while the conversion is in progress. how- ever, once the conversion is complete, there is no way of writing to the part unless the convst pin is exercised. the convst signal triggers the sync signal low which allows read/write op- erations to take place. sync must be low to perform read/write operations. the sync is triggered low by the convst signal rising edge or setting the convst bit in the control register to 1. therefore if there is not full control of the convst pin the user may end up getting locked out. serial interface mode ? power-on, apply clkin signal, wait 150ms for automatic calibration din connected to dgnd no yes start wait for busy signal to go low pulse convst pin read data during conversion ? wait approximately 200ns after convst rising edge apply sync (if required), sclk and read conversion result on dout pin pulse convst pin sync automatically goes low after convst rising edge sclk automatically active, read conversion result on dout pin 4, 5 2, 3 figure 40. flowchart for setting up and reading from the ad7851 configuring the ad7851 ad7851 as a read-only adc the ad7851 contains fourteen on-chip registers which can be accessed via the serial interface. in the majority of applications it will not be necessary to access all of these registers. figure 40 outlines a flowchart of the sequence which is used to configure the ad7851 as a read-only adc. in this case there is no writ- ing to the on-chip registers and only the conversion result data is read from the part. interface mode 1 cannot be used in this case as it is necessary to write to the control register to set interface mode 1. here the clkin signal is applied directly after power- on, the clkin signal must be present to allow the part to per- form a calibration. this automatic calibration will be completed approximately 150 ms after power-on.
ad7851 C28C rev. a serial interface mode ? no yes transfer data during conversion ? apply sync (if required), sclk, read current conversion result on dout pin, and write all 0s on din pin wait for busy signal to go low or wait for busy bit = 0 apply sync (if required), sclk, write to control register setting convst bit to 1, read current conversion result on dout pin 2, 3 initiate conversion in software ? wait approximately 200ns after convst rising edge apply sync (if required), sclk, read previous conversion result on dout pin, and write all 0s on din pin no yes transfer data during conversion apply sync (if required), sclk, write to control register setting convst bit to 1, read previous conversion result on dout pin (see note) yes no note: when using the software conversion start and transferring data during conversion the user must ensure the control register write operation extends beyond the falling edge of busy. the falling edge of busy resets the convst bit to 0 and only after this time can it be reprogrammed to 1 to start the next conversion. start power-on, apply clkin signal, wait 150ms for automatic calibration pulse convst pin wait for busy signal to go low or wait for busy bit = 0 figure 41. flowchart for setting up, reading, and writing in interface modes 2 and 3 writing to the ad7851 for accessing the on-chip registers it is necessary to write to the part. to enable serial interface mode 1, the user must also write to the part. figure 41 through 43 outline flowcharts of how to configure the ad7851 for each of the different serial interface modes. the continuous loops on all diagrams indicate the se- quence for more than one conversion. the options of using a hardware (pulsing the convst pin) or software (setting the convst bit to 1) conversion start, and reading/writing during or after conversion are shown in figures 41 and 42. if the convst pin is never used then it should be tied to dv dd per- manently. where reference is made to the busy bit equal to a logic 0, to indicate the end of conversion, the user in this case would poll the busy bit in the status register. interface modes 2 and 3 configuration figure 41 shows the flowchart for configuring the part in inter- face modes 2 and 3. for these interface modes, the read and write operations take place simultaneously via the serial port. writing all 0s ensures that no valid data is written to any of the registers. when using the software conversion start and transfer- ring data during conversion, note must be obeyed.
C29C rev. a ad7851 interface mode 1 configuration figure 42 shows the flowchart for configuring the part in inter- face mode 1. this mode of operation can only be enabled by writing to the control register and setting the 2/ 3 mode bit. reading and writing cannot take place simultaneously in this mode as the din pin is used for both reading and writing. serial interface mode ? power-on, apply clkin signal, wait 150ms for automatic calibration no yes wait for busy signal to go low or wait for busy bit = 0 read data during conversion ? apply sync (if required), sclk, read current conversion result on din pin 1 initiate conversion in software ? wait approximatly 200ns after convst rising edge or after end of control register write apply sync (if required), sclk, read previous conversion result on din pin no yes apply sync (if required), sclk, write to control register setting the two-wire mode and convst bit to 1 start apply sync (if required), sclk, write to control register setting the two-wire mode pulse convst pin figure 42. flowchart for setting up, reading, and writing in interface mode 1 interface modes 4 and 5 configuration figure 43 shows the flowchart for configuring the ad7851 in interface modes 4 and 5, the self-clocking modes. in this case it is not recommended to use the software conversion start option. the read and write operations always occur simultaneously and during conversion. power-on, apply clkin signal, wait 150ms for automatic calibration sync automatically goes low after convst rising edge pulse convst pin sclk automatically active, read current conversion result on dout pin, write to control register on din pin 4, 5 start serial interface mode ? figure 43. flowchart for setting up, reading, and writing in interface modes 4 and 5
ad7851 C30C rev. a (8xc51/l51) /pic17c42 p3.0/dt p3.1/ck ad7851 convst clkin sclk din sync sm1 sm2 polarity optional 7mhz/6mhz busy ( int0 /p3.2)/int dv dd for 8xc51/l51 dgnd for pic17c42 master slave optional figure 45. 8xc51/pic16c42 interface ad7851 to 68hc11/16/l11 / pic16c42 interface figure 46 shows the ad7851 spi/qspi interface to the 68hc11/16/l11/pic16c42. the sync line is not used and is tied to dgnd. the m controller is configured as the master, by setting the mstr bit in the spcr to 1, and thus provides the serial clock on the sck pin. for all the m controllers, the cpol bit is set to 1 and for the 68hc11/16/l11, the cpha bit is set to 1. the clkin and convst signals can be supplied from the m controller or from separate sources. the busy signal can be used as an interrupt to tell the m controller when the conver- sion is finished, then the reading and writing can take place. if required the reading and writing can take place during conver- sion and there will be no need for the busy signal in this case. for no writing to the part then the din pin can be tied perma- nently low. for the 68hc16 and the qspi interface the sm2 pin should be tied high and the ss line tied to the sync pin. the microsequencer on the 68hc16 qspi port can be used for performing a number of read and write operations independent of the cpu and storing the conversion results in memory with- out taxing the cpu. the typical sequence of events would be writing to the control register via the din line setting a conver- sion start and at the same time reading data from the previous conversion on the dout line, wait for the conversion to be finished (3.25 m s with 6 mhz clkin), and then repeat the sequence. the maximum serial frequency will be determined by the data access and hold times of the m controllers and the ad7851. 68hc11/l11/16 sck ss ad7851 convst clkin sclk dout busy sm1 sm2 polarity optional 7mhz/6mhz sync miso din at dgnd for no writing to part master slave din dv dd optional irq mosi dv dd for hc11, spi dgnd for hc16, qspi dv dd spi hc16, qspi figure 46. 68hc11 and 68hc16 interface microprocessor interfacing in many applications, the user may not require the facility of writing to the on-chip registers. the user may just want to hardwire the relevant pins to the appropriate levels and read the conversion result. in this case the din pin can be tied low so that the on-chip registers are never used. now the part will op- erate as a nonprogrammable analog to digital converter where the convst is applied, a conversion is performed and the re- sult may be read using the sclk to clock out the data from the output register on to the dout pin. note that the din pin cannot be tied low when using the two-wire interface mode of operation. the sclk can also be connected to the clkin pin if the user does not want to have to provide separate serial and master clocks in interface modes 1, 2, and 3. with this arrangement the sync signal must be low for 16 sclk cycles in interface modes 1 and 2 for the read and write operations. for interface mode 3 the sync can be low for more than 16 sclk cycles for the read and write operations. note that in interface modes 4 and 5 the clkin and sclk cannot be tied together as the sclk is an output and the clkin is an input. din dout sync convst clkin sclk ad7851 7 mhz/6mhz master clock sync signal to gate the sclk serial data output conversion start figure 44. simplified interface diagram with din grounded and sclk tied to clkin ad7851 to 8xc51/pic17c42 interface figure 45 shows the ad7851 interface to the 8xc51/pic17c42. the 8xc51/pic17c42 only run at 5 v. the 8xc51 is in mode 0 operation. this is a two-wire interface consisting of the sclk and the din which acts as a bidirectional line. the sync is tied low. the busy line can be used to give an interrupt driven system but this would not normally be the case with the 8xc51/ pic17c42. for the 8xc51 12 mhz version, the serial clock will run at a maximum of 1 mhz so that the serial interface to the ad7851 will only be running at 1 mhz. the clkin signal must be provided separately to the ad7851 from a port line on the 8xc51 or from a source other than the 8xc51. here the sclk cannot be tied to the clkin as the 8xc51 only pro- vides a noncontinuous serial clock. the convst signal can be provided from an external timer or conversion can be started in software if required. the sequence of events would typically be writing to the control register via the din line setting a conver- sion start and the 2-wire interface mode (this would be per- formed in two 8-bit writes), wait for the conversion to be finished (3.25 m s with 6 mhz clkin), read the conversion re- sult data on the din line (this would be performed in two 8-bit reads), and then repeat the sequence. the maximum serial fre- quency will be determined by the data access and hold times of the 8xc51/pic16c42 and the ad7851.
C31C rev. a ad7851 ad7851 to adsp-21xx interface figure 47 shows the ad7851 interface to the adsp-21xx. the adsp-21xx is the slave and the ad7851 is the master. the ad7851 is in interface mode 5. for the adsp-21xx, the bits in the serial port control register should be set up as tfsr = rfsr = 1 (need a frame sync for every transfer), slen = 15 (16-bit word length), tfsw = rfsw = 1 (alternate framing mode for transmit and receive operations), invrfs = invtfs = 1 (active low rfs and tfs), irfs = itfs = 0 (external rfs and tfs), and isclk = 0 (external serial clock). the clkin and convst signals could be supplied from the adsp-21xx or from an external source. the ad7851 supplies the sclk and the sync signals to the adsp-21xx and the reading and writing takes place during conversion. the busy signal only indicates when the conversion is finished and may not be required. the data access and hold times of the adsp- 21xx and the ad7851 allows for a clkin of 7 mhz/6 mhz with a 5 v supply. ad7851 convst clkin sclk dout busy sm1 sm2 polarity optional 7mhz/6mhz sync rfs din at dgnd for no writing to part slave master optional din dv dd optional irq dt tfs adsp-21xx dr sck figure 47. adsp-21xx interface ad7851 to dsp56000/1/2/l002 interface figure 48 shows the ad7851 to dsp56000/1/2/l002 interface. here the dsp5600x is the master and the ad7851 is the slave. the ad7851 is in interface mode 3. the setting of the bits in the registers of the dsp5600x would be for synchronous opera- tion (syn = 1), internal frame sync (scd2 = 1), internal clock (sckd = 1), 16-bit word length (wl1 = 1, wl0 = 0), frames sync only active at beginning of the transfer (fsl1 = 0, fsl0 = 1). a gated clock can be used (gck = 1) or if the sclk is to be tied to the clkin of the ad7851, then there must be a con- tinuous clock (gck = 0). again the data access and hold times of the dsp5600x and the ad7851 should allow for an sclk of 7 mhz/6 mhz. ad7851 convst clkin sclk dout busy sm1 sm2 polarity optional 7mhz/6mhz sync din at dgnd for no writing to part slave optional din dv dd optional dsp 56000/1/2/l002 srd sck sc2 master irq std figure 48. dsp56000/1/2 interface ad7851 to tms320c20/25/5x/lc5x interface figure 49 shows the ad7851 to the tms320cxx interface. the ad7851 is the master and operates in interface mode 5. for the tms320cxx the clkx, clkr, fsx, and fsr pins should all be configured as inputs. the clkx and the clkr should be connected together as sh ould the fsx and fsr. since the ad7851 is the master and the reading and writing occurs during the conversion, the busy only indicates when the con- version is finished and thus may not be required. again the data access and hold times of the tms320cxx and the ad7851 al- lows for a clkin of 7 mhz/6 mhz. ad7851 convst clkin sclk dout busy sm1 sm2 polarity optional 7mhz/6mhz sync din at dgnd for no writing to part slave master optional din dv dd optional dt fsx int0 tms320c20/ 25/5x/lc5x dr clkr fsr clkx figure 49. tms320c20/25/5x interface
ad7851 C32C rev. a evaluating the ad7851 performance the recommended layout for the ad7851 is outlined in the evaluation board for the ad7851. the evaluation board pack- age includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from the pc via the eval-control board. the eval-con- trol board can be used in conjunction with the ad7851 evaluation board, as well as many other analog devices evalua- tion boards ending in the cb designator, to demonstrate/evalu- ate the ac and dc performance of the ad7851. the software allows the user to perform ac (fast fourier trans- form) and dc (histogram of codes) tests on the ad7851. it also gives full access to all the ad7851 on-chip registers allowing for various calibration and power-down options to be programmed. ad785x family all parts are 12 bits, 200 ksps, 3.0 v to 5.5 v. ad7853 C single channel serial ad7854 C single channel parallel ad7858 C eight channel serial ad7859 C eight channel parallel application hints grounding and layout the analog and digital supplies to the ad7851 are independent and separately pinned out to minimize coupling between the analog and digital sections of the device. the part has very good immunity to noise on the power supplies as can be seen by the psrr versus frequency graph. however, care should still be taken with regard to grounding and layout. the printed circuit board that houses the ad7851 should be de- signed such that the analog and digital sections are separated and confined to certain areas of the board. this facilitates the use of ground planes that can be separated easily. a minimum etch technique is generally best for ground planes as it gives the best shielding. digital and analog ground planes should only be joined in one place. if the ad7851 is the only device requiring an agnd to dgnd connection, then the ground planes should be connected at the agnd and dgnd pins of the ad7851. if the ad7851 is in a system where multiple devices require agnd to dgnd connections, the connection should still be made at one point only, a star ground point which should be established as close as possible to the ad7851. avoid running digital lines under the device as these will couple noise onto the die. the analog ground plane should be allowed to run under the ad7851 to avoid noise coupling. the power supply lines to the ad7851 should use as large a trace as pos- sible to provide low impedance paths and reduce the effects of glitches on the power supply line. fast switching signals like clocks should be shielded with digital ground to avoid radiating noise to other sections of the board and clock signals should never be run near the analog inputs. avoid crossover of digital and analog signals. traces on opposite sides of the board should run at right angles to each other. this will reduce the effects of feedthrough through the board. a microstrip technique is by far the best but is not always possible with a double-sided board. in this technique, the component side of the board is dedicated to ground planes while signals are placed on the solder side. good decoupling is also important. all analog supplies should be decoupled with 10 m f tantalum in parallel with 0.1 m f ca- pacitors to agnd. all digital supplies should have a 0.1 m f disc ceramic capacitor to agnd. to achieve the best from these decoupling components, they must be placed as close as possible to the device, ideally right up against the device. in systems where a common supply voltage is used to drive both the av dd and dv dd of the ad7851, it is recommended that the systems av dd supply is used. in this case there should be a 10 w resistor between the av dd pin and dv dd pin. this supply should have the recommended analog supply decoupling capacitors between the av dd pin of the ad7851 and agnd and the recommended digital supply decoupling capacitor between the dv dd pin of the ad7851 and dgnd.
C33C rev. a ad7851 page index topic page features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 general description . . . . . . . . . . . . . . . . . . . . . . . . . 1 product highlights . . . . . . . . . . . . . . . . . . . . . . . . . 1 specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 timing specifications . . . . . . . . . . . . . . . . . . . . . . . 4 typical timing diagrams . . . . . . . . . . . . . . . . . . . . 5 absolute maximum ratings . . . . . . . . . . . . . . . . . 6 ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 pin function description . . . . . . . . . . . . . . . . . . . 8 ad7851 on-chip registers . . . . . . . . . . . . . . . . . . . . . 9 addressing the on-chip registers . . . . . . . . . . . . . . . . . . . 9 writing/reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 control register . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 calibration registers . . . . . . . . . . . . . . . . . . . . . . 12 addressing the calibration registers . . . . . . . . . . . . . . . . 12 writing to/reading from the calibration registers . . . . . . 12 adjusting the offset calibration register . . . . . . . . . . . . . 13 adjusting the gain calibration registers . . . . . . . . . . . . . 13 circuit information . . . . . . . . . . . . . . . . . . . . . . . . 14 converter details . . . . . . . . . . . . . . . . . . . . . . . . . . 14 typical connection diagram . . . . . . . . . . . . . . . 14 analog input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 acquisition time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 dc/ac applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 input ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 transfer functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 reference section . . . . . . . . . . . . . . . . . . . . . . . . . . 17 ad7851 performance curves . . . . . . . . . . . . . . . . 17 power-down options . . . . . . . . . . . . . . . . . . . . . . . . 18 power-up times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 using an external reference . . . . . . . . . . . . . . . . . . . . . . 19 using the internal (on-chip) reference . . . . . . . . . . . . . 19 power vs. throughput rate . . . . . . . . . . . . . . . . 19 calibration section . . . . . . . . . . . . . . . . . . . . . . . . 20 calibration overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 automatic calibration on power-on . . . . . . . . . . . . . . . . 20 self-calibration description . . . . . . . . . . . . . . . . . . . . . . . 20 self-calibration timing . . . . . . . . . . . . . . . . . . . . . . . . . . 21 system calibration description . . . . . . . . . . . . . . . . . . . . 21 system gain and offset interaction . . . . . . . . . . . . . . . . . 22 system calibration timing . . . . . . . . . . . . . . . . . . . . . . . 22 serial interface summary . . . . . . . . . . . . . . . . . . 23 resetting the serial interface . . . . . . . . . . . . . . . . . . . . . . 23 detailed timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 mode 1 (2-wire 8051 interface) . . . . . . . . . . . . . . . . . . . 24 mode 2 (3-wire spi/qspi interface mode) . . . . . . . . . . . 25 mode 3 (qspi interface mode) . . . . . . . . . . . . . . . . . . . . 25 mode 4 and 5 (self-clocking modes) . . . . . . . . . . . . . . . 26 configuring the ad7851 . . . . . . . . . . . . . . . . . . . . . 27 ad7851 as a read-only adc . . . . . . . . . . . . . . . . . . . . . 27 writing to the ad7851 . . . . . . . . . . . . . . . . . . . . . . . . . . 28 interface modes 2 and 3 configuration . . . . . . . . . . . . . . 28 interface mode 1 configuration . . . . . . . . . . . . . . . . . . . . 29 interface modes 4 and 5 configuration . . . . . . . . . . . . . . 29 microprocessor interfacing . . . . . . . . . . . . . . . 30 ad7851 C 8xc51/pic17c42 interface . . . . . . . . . . . . . . . . 30 ad7851 C 68hc11/16/l11/pic16c42 interface . . . . . . . . 30 ad7851 C adsp-21xx interface . . . . . . . . . . . . . . . . . . . . . 31 ad7851 C dsp56000/1/2/l002 interface . . . . . . . . . . . . . . 31 ad7851 C tms320c20/25/5x/lc5x interface . . . . . . . . . . 31 applications hints . . . . . . . . . . . . . . . . . . . . . . . . . . 32 grounding and layout . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 evaluating the ad7851 performance . . . . . . . . . . . . . . . . 32 index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . 34 table index # title page i write register addressing . . . . . . . . . . . . . . . . . . . . . . . 9 ii read register addressing . . . . . . . . . . . . . . . . . . . . . . . 9 iii calibration selection . . . . . . . . . . . . . . . . . . . . . . . . . . 10 iv calibrating register addressing . . . . . . . . . . . . . . . . . . 12 v analog input connections . . . . . . . . . . . . . . . . . . . . . . 16 vi power management options . . . . . . . . . . . . . . . . . . . . 18 vii power consumption vs. throughput . . . . . . . . . . . . . . 20 viii calibration times . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 ix sclk active edges . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 x interface mode description . . . . . . . . . . . . . . . . . . . . . 23
ad7851 C34C rev. a outline dimensions dimensions shown in inches and (mm). 24-pin plastic dip (n-24) 24 112 13 0.280 (7.11) 0.240 (6.10) pin 1 1.275 (32.30) 1.125 (28.60) 0.150 (3.81) min 0.200 (5.05) 0.125 (3.18) seating plane 0.022 (0.558) 0.014 (0.356) 0.060 (1.52) 0.015 (0.38) 0.210 (5.33) max 0.070 (1.77) 0.045 (1.15) 0.100 (2.54) bsc 0.325 (8.25) 0.300 (7.62) 0.015 (0.381) 0.008 (0.204) 0.195 (4.95) 0.115 (2.93) 24-pin small outline package (r-24) 24 13 12 1 0.6141 (15.60) 0.5985 (15.20) 0.4193 (10.65) 0.3937 (10.00) 0.2992 (7.60) 0.2914 (7.40) pin 1 seating plane 0.0118 (0.30) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.1043 (2.65) 0.0926 (2.35) 0.0500 (1.27) bsc 0.0125 (0.32) 0.0091 (0.23) 0.0500 (1.27) 0.0157 (0.40) 8 0 0.0291 (0.74) 0.0098 (0.25) x 45 24-pin shrink small outline package (rs-24) 24 1 13 12 0.328 (8.33) 0.318 (8.08) 0.311 (7.9) 0.301 (7.64) 0.212 (5.38) 0.205 (5.207) pin 1 seating plane 0.008 (0.203) 0.002 (0.050) 0.07 (1.78) 0.066 (1.67) 0.0256 (0.65) bsc 0.078 (1.98) 0.068 (1.73) 0.015 (0.38) 0.010 (0.25) 0.009 (0.229) 0.005 (0.127) 0.037 (0.94) 0.022 (0.559) 8 0
C35C
c2166C18C8/96 printed in u.s.a. C36C

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